STM32F405 datasheet(9/204 Pages) STMICROELECTRONICS

9 / 204 page

DS8626 Rev 9

9/203

STM32F405xx, STM32F407xx

List of figures

Figure 1.

Compatible board design between STM32F10xx/STM32F40xxx for LQFP64 . . . . . . . . . . 16

Figure 2.

Compatible board design STM32F10xx/STM32F2/STM32F40xxx

for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3.

Compatible board design between STM32F10xx/STM32F2/STM32F40xxx

for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4.

Compatible board design between STM32F2 and STM32F40xxx

for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5.

STM32F40xxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6.

Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7.

Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25

Figure 8.

PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9.

Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10.

Startup in regulator OFF mode: slow VDD slope

- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.

Startup in regulator OFF mode: fast VDD slope

- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12.

STM32F40xxx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13.

STM32F40xxx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14.

STM32F40xxx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15.

STM32F40xxx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 16.

STM32F40xxx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 17.

STM32F40xxx WLCSP90 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 18.

STM32F40xxx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 19.

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 20.

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 21.

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 22.

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 23.

External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 24.

Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 87

Figure 25.

Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 87

Figure 26.

Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 88

Figure 27.

Typical current consumption versus temperature, Run mode, code with data

processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 88

Figure 28.

Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 91

Figure 29.

Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 92

Figure 30.

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 31.

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 32.

Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 33.

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 34.

ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 35.

PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 36.

PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 37.

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 38.

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 39.

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

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