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STM32F405 数据表(PDF) 82 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 82 Page - STMicroelectronics |
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82 / 204 page  Electrical characteristics STM32F405xx, STM32F407xx 82/203 DS8626 Rev 9 5.3.2 VCAP_1/VCAP_2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP_1/VCAP_2 pins. CEXT is specified in Table 16. Figure 23. External capacitor CEXT 1. Legend: ESR is the equivalent series resistance. 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. 5.3.4 Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 16. VCAP_1/VCAP_2 operating conditions(1) 1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 µF ESR ESR of external capacitor < 2 Ω MS19044V2 ESR R Leak C Table 17. Operating conditions at power-up / power-down (regulator ON) Symbol Parameter Min Max Unit tVDD VDD rise time rate 20 ∞ µs/V VDD fall time rate 20 ∞ Table 18. Operating conditions at power-up / power-down (regulator OFF)(1) 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below minimum value of V12. Symbol Parameter Conditions Min Max Unit tVDD VDD rise time rate Power-up 20 ∞ µs/V VDD fall time rate Power-down 20 ∞ tVCAP VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞ VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞ |
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