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STM32F405 数据表(PDF) 28 Page - STMicroelectronics

部件名 STM32F405
功能描述  Arm® Cortex®-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  204 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F405 数据表(HTML) 28 Page - STMicroelectronics

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Description
STM32F405xx, STM32F407xx
28/203
DS8626 Rev 9
The following conditions must be respected:
•
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10).
•
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see
Figure 11).
•
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then
a reset must be asserted on PA0 pin.
Note:
The minimum value of V12 depends on the maximum frequency targeted in the application
(see Table 14: General operating conditions).
Figure 10. Startup in regulator OFF mode: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.
ai18491e
VDD
time
Min V12
PDR = 1.7 V or 1.8 V
(2)
VCAP_1/VCAP_2
V12
NRST
time



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