STM32F405 datasheet(24/204 Pages) STMICROELECTRONICS

24 / 204 page

Description

STM32F405xx, STM32F407xx

24/203

DS8626 Rev 9

clock entry is available when necessary (for example if an indirectly used external oscillator

fails).

Several prescalers allow the configuration of the three AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB

buses is 168 MHz while the maximum frequency of the high-speed APB domains is

84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class

performance. In this case, the I2S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

2.2.13

Boot modes

At startup, boot pins are used to select one out of three boot options:

•

Boot from user Flash

•

Boot from system memory

•

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB

OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

2.2.14

Power supply schemes

•

VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins.

•

VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Refer to Figure 21: Power supply scheme for more details.

Note:

VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced

temperature range, and with the use of an external power supply supervisor (refer to

Section : Internal reset OFF).

Refer to Table 2 in order to identify the packages supporting this option.

2.2.15

Power supply supervisor

Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On all other packages, the power supply supervisor is always

enabled.

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

reached, the option byte loading process starts, either to confirm or modify default BOR

threshold levels, or to disable BOR permanently. Three BOR thresholds are available

through option bytes. The device remains in reset mode when VDD is below a specified

threshold, VPOR/PDR or VBOR, without the need for an external reset circuit.

STM32F405 数据表(PDF) 24 Page - STMicroelectronics

STM32F405 数据表(HTML) 24 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载