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STM32L082KB 数据表(PDF) 104 Page - STMicroelectronics |
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STM32L082KB 数据表(HTML) 104 Page - STMicroelectronics |
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104 / 132 page ![]() Electrical characteristics STM32L082xx 104/132 DS10688 Rev 7 Table 72. SPI characteristics in voltage Range 2 (1) Symbol Parameter Conditions Min Typ Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode -- 8 MHz Slave mode Transmitter 1.65<VDD<3.6V 8 Slave mode Transmitter 2.7<VDD<3.6V 8(2) Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - ns th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 tsu(MI) Data input setup time Master mode 0 - - tsu(SI) Slave mode 3 - - th(MI) Data input hold time Master mode 11 - - th(SI) Slave mode 4.5 - - ta(SO Data output access time Slave mode 18 - 52 tdis(SO) Data output disable time Slave mode 12 - 42 tv(SO) Data output valid time Slave mode - 20 56.5 tv(MO) Master mode - 5 9 th(SO) Data output hold time Slave mode 13 - - th(MO) Master mode 3 - - 1. Guaranteed by characterization results. 2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. |
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