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STM32H757AI 数据表(PDF) 169 Page - STMicroelectronics |
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STM32H757AI 数据表(HTML) 169 Page - STMicroelectronics |
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169 / 251 page  DS12931 Rev 1 169/251 STM32H757xI Electrical characteristics 230 Synchronous waveforms and timings Figure 32 through Figure 35 represent synchronous waveforms and Table 86 through Table 89 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable • MemoryType = FMC_MemoryType_CRAM • WriteBurst = FMC_WriteBurst_Enable • CLKDivision = 1 • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Table 84. Asynchronous multiplexed PSRAM/NOR write timings(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck ns tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck –1 Tfmc_ker_ck +0.5 tw(NWE) FMC_NWE low time 2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck –0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5 tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck + 1 th(AD_NADV) FMC_AD(adress) valid hold time after FMC_NADV high) Tfmc_ker_ck +0.5 - th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck +0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck – 0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +2 th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck +0.5 - Table 85. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) 1. Guaranteed by characterization results. 2. NWAIT pulse width is equal to 1 AHB cycle. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 9Tfmc_ker_ck –1 9Tfmc_ker_ck ns tw(NWE) FMC_NWE low time 7Tfmc_ker_ck –0.5 7Tfmc_ker_ck +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck +11 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck +11.5 - |
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