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STM32H757AI 数据表(PDF) 170 Page - STMicroelectronics |
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STM32H757AI 数据表(HTML) 170 Page - STMicroelectronics |
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170 / 251 page  Electrical characteristics STM32H757xI 170/251 DS12931 Rev 1 In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values: • For 2.7 V<VDD<3.6 V, FMC_CLK = 125 MHz at 20 pF • For 1.8 V<VDD<1.9 V, FMC_CLK = 100 MHz at 20 pF • For 1.62 V<VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF Figure 32. Synchronous multiplexed NOR/PSRAM read timings FMC_CLK FMC_NEx FMC_NADV FMC_A[25:16] FMC_NOE FMC_AD[15:0] AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKH-NExH) t d(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKH-AIV) td(CLKL-NOEL) td(CLKH-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) MS32757V1 |
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