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KSZ9567RTXI-TR 数据表(PDF) 177 Page - Microchip Technology |
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KSZ9567RTXI-TR 数据表(HTML) 177 Page - Microchip Technology |
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177 / 232 page ![]() 2017-2019 Microchip Technology Inc. DS00002329D-page 177 KSZ9567R 5.2.8 PORT N: PORT SWITCH EGRESS CONTROL REGISTERS (0xN900 - 0xN9FF) 5.2.8.1 Port Transmit Queue Index Register This register holds an index value that is used when accessing several registers that follow. This register may be accessed as an 8-bit register, with bits [7:0] located at address 0xN903. 5.2.8.2 Port Transmit Queue PVID Register This register may be accessed as an 8-bit register, with bits [7:0] located at address 0xN903. Address: 0xN900 - 0xN903 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:2 RESERVED RO 0x00000000 1:0 Queue Index Points to the queue number for subsequent queue configuration registers. R/W 00 Address: 0xN904 - 0x907 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:1 RESERVED RO 0x00000000 0 Port VID Replacement 1 = For any egress packet with a non-zero VLAN ID, replace the VID with the port default VID from the Port Default Tag 0 Register and Port Default Tag 1 Register. If double tagging is enabled, it is the ISP tag ID that will be replaced. 0 = Do not replace the VID. R/W 0b |
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