KSZ9567RTXI-TR datasheet(64/232 Pages) MICROCHIP

64 / 232 page

KSZ9567R

DS00002329D-page 64

 2017-2019 Microchip Technology Inc.

• Supports network data rates of either 10Mbps or 100Mbps.

• Uses a single 50MHz clock reference (provided internally or externally) for both transmit and receive data.

• Uses independent 2-bit wide transmit and receive data paths.

• Contains two distinct groups of signals: one for transmission and the other for reception.

The user selects one of the two RMII clocking modes by setting the appropriate strapping option. The clocking mode is

selected separately for ports 6 and 7.

While in RMII Normal Mode, the port will require an external 50MHz signal to be input to TX_CLKx/REFCLKIx from an

external source. This mode is selected by strapping the appropriate pin (RXD6_1 for port 6; RXD7_1 for port 7) high

during reset.

While in RMII Clock Mode, the port will output a 50MHz clock on RX_CLKx/REFCLKOx, which is derived from the

25MHz crystal or oscillator attached to the XI clock input. The TX_CLKx/REFCLKIx input is unused in this mode. This

mode is selected by strapping the appropriate pin (RXD6_1 for port 6; RXD7_1 for port 7) low during reset.

Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional configuration strap information.

Table 4-30 describes the signals used by the RMII interface. Refer to the RMII specification for full details on the signal

descriptions.

A device port in RMII mode may connect to either an external MAC device (such as a host processor) or to an external

PHY; but unlike MII, RMII does not provide separate PHY and MAC modes of operation. However, it is necessary to

connect the pins properly.

TABLE 4-30:

RMII SIGNAL DESCRIPTIONS

RMII Signal

Name

(per spec)

RMII Signal

(per KSZ9567R)

Pin Direction

(with respect to

PHY, KSZ9567R)

Pin Direction

(with respect to

MAC)

RMII Signal Description

REF_CLK

REFCLKI6

REFCLKI7

Input

Input or Output

Synchronous 50MHz reference clock,

when port is in RMII Normal Mode

n/a

REFCLKO6

REFCLKO7

Output

Input

Synchronous 50MHz reference clock,

when port is in RMII Clock Mode

TX_EN

TX_EN6

TX_EN7

Input

Output

Transmit Enable

TXD[1:0]

TXD6_[1:0]

TXD7_[1:0]

Input

Output

Transmit Data Bit [1:0]

CRS_DV

RX_DV6

RX_DV7

Output

Input

Carrier Sense / Receive Data Valid

RX_ER

RX_ER6

RX_ER7

Output

Input or

not required

Receive Error

RXD[1:0]

RXD6_[1:0]

RXD7_[1:0]

Output

Input

Receive Data Bit [1:0]

TABLE 4-31:

RMII CONNECTION TO EXTERNAL MAC

RMII Interface Signals Description

KSZ9567R Signals

External MAC Device Signals

Transmit Enable

TX_ENx (input)

TX_EN (output)

Transmit Data Bits [1:0]

TXDx_[1:0] (input)

TXD[1:0] (output)

Reference Clock

REFCLKIx (input)

or REFCLKOx (output)

REF_CLK

(input or output)

Carrier Sense Data Valid

RX_DVx (output)

CRS_DV (input)

Receive Error

RX_ERx (output)

RX_ER (input)

Receive Data Bits [1:0]

RXDx_[1:0] (output)

RXD[1:0] (input)

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