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KSZ9567RTXI-TR 数据表(PDF) 52 Page - Microchip Technology |
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KSZ9567RTXI-TR 数据表(HTML) 52 Page - Microchip Technology |
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52 / 232 page  KSZ9567R DS00002329D-page 52 2017-2019 Microchip Technology Inc. The egress of SR class traffic from the high priority queue(s) is regulated at each queue by a credit-based traffic shaper as discussed below. If the SR traffic streams do not exceed their reserved bandwidth, then the traffic shaper will ensure that the packets egress in a relatively uniform manner. The 802.1AS standard, which ensures node synchronization in an AVB network, relies heavily on the IEEE 1588 stan- dard for PTP. It defines a specific profile for 1588, and adds certain other requirements in the context of 802.1Q. The resulting entity is referred to as generalized PTP (gPTP). Section 4.5, "IEEE 1588 Precision Time Protocol" discusses IEEE 1588 and 802.1AS together. The device provides two egress traffic shaping options. The IEEE 802.1Qav Credit-Based Traffic Shaper provides traffic shaping as defined in IEEE 802.1Qav. This is configurable on a per-queue basis. Each port also has a Time Aware Traf- fic Scheduler (TAS) that provides periodic timing windows for transmission of time sensitive traffic class data. The shaper and scheduler options and details are individually configurable for each egress port. 4.7 NAND Tree Support The KSZ9567R provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree is a chain of nested NAND gates in which each KSZ9567R digital I/O (NAND tree input) pin is an input to one NAND gate along the chain. At the end of the chain, the INTRP_N pin provides the output for the last NAND gate. The NAND tree test process includes: • Enabling NAND tree mode • Pulling all NAND tree input pins high • Driving low each NAND tree input pin sequentially per the NAND tree pin order, starting with the first row of Table 4-23. • Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input driven low. TABLE 4-23: NAND TREE TEST PIN ORDER NAND Tree Sequence Pin Number Pin Name NAND Tree Description 148 TX_CLK6/REFCLKI6 Input 249 TX_EN6/TX_CTL6 Input 350 TX_ER6 Input 451 COL6 Input 552 TXD6_3 Input 653 TXD6_2 Input 754 TXD6_1 Input 855 TXD6_0 Input 957 RX_CLK6/REFCLKO6 Input 10 58 RX_DV6/CRS_DV6/RX_CTL6 Input 11 59 RX_ER6 Input 12 60 CRS6 Input 13 62 RXD6_3 Input 14 63 RXD6_2 Input 15 64 RXD6_1 Input 16 65 RXD6_0 Input 17 66 TX_CLK7/REFCLKI7 Input 18 67 TX_EN7/TX_CTL7 Input 19 68 TX_ER7 Input 20 69 COL7 Input 21 70 TXD7_3 Input 22 71 TXD7_2 Input 23 72 TXD7_1 Input |
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