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KSZ9567RTXI-TR 数据表(PDF) 53 Page - Microchip Technology |
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KSZ9567RTXI-TR 数据表(HTML) 53 Page - Microchip Technology |
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53 / 232 page  2017-2019 Microchip Technology Inc. DS00002329D-page 53 KSZ9567R The following procedure can be used to check for faults on the KSZ9567R digital I/O pin connections to the board: 1. Enable NAND tree mode via the LED2_1, LED2_0, and LED4_0 configuration strap pins option. 2. Use board logic to drive all KSZ9567R NAND tree input pins high and verify that the INTRP_N pin output is high. 3. Use board logic to drive each NAND tree input pin, per the NAND Tree pin order, as follows: a) Toggle the first pin in the NAND tree sequence (TX_CLK6/REFCLKI6) from high to low, and verify the INTRP_N pin switches from high to low to indicate that the first pin is connected properly. b) Leave the first pin (TX_CLK6/REFCLKI6) low. c) Toggle the second pin in the NAND tree sequence (TX_EN6/TX_CTL6) from high to low, and verify the INTRP_N pin switches from low to high to indicate that the second pin is connected properly. d) Leave the first pin (TX_CLK6/REFCLKI6) and the second pin (TX_EN6/TX_CTL6) low. e) Toggle the third pin in the NAND tree sequence (TX_ER6) from high to low, and verify the INTRP_N pin switches from high to low to indicate that the third pin is connected properly. f) Continue with this sequence until all KSZ9567R NAND tree input pins have been toggled. Each KSZ9567R NAND tree input pin must cause the INTRP_N output pin to toggle high-to-low or low-to-high to indi- cate a good connection. If the INTRP_N pin fails to toggle when the KSZ9567R input pin toggles from high to low, the input pin has a fault. 24 73 TXD7_0 Input 25 75 RX_CLK7/REFCLKO7 Input 26 76 RX_DV7/CRS_DV7/RX_CTL7 Input 27 78 RX_ER7 Input 28 79 CRS7 Input 29 80 RXD7_3 Input 30 81 RXD7_2 Input 31 82 RXD7_1 Input 32 83 RXD7_0 Input 33 85 LED4_0 Input 34 86 LED4_1 Input 35 88 LED3_0 Input 36 89 LED3_1 Input 37 90 GPIO_1 Input 38 91 LED2_0 Input 39 92 LED2_1 Input 40 93 PME_N Input 41 96 RESET_N Input 42 97 SDO Input 43 98 SDI/SDA/MDIO Input 44 100 SCS_N Input 45 101 SCL/MDC Input 46 102 LED5_0 Input 47 103 LED5_1 Input 48 105 LED1_0 Input 49 106 LED1_1 Input 50 94 INTRP_N Output TABLE 4-23: NAND TREE TEST PIN ORDER (CONTINUED) NAND Tree Sequence Pin Number Pin Name NAND Tree Description |
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