KSZ9567RTXI-TR datasheet(39/232 Pages) MICROCHIP

39 / 232 page

 2017-2019 Microchip Technology Inc.

DS00002329D-page 39

KSZ9567R

By default, tail tagging is disabled. To enable it, set the Tail Tag Enable bit in one of the Port Operation Control 0 Register

at address 0xN020 for port “N”. When this bit is set for one port, that port is referred to as the “host” port. Do not set the

Tail Tag Enable bit for more than one port.

When IEEE 1588 Precision Time Protocol (PTP) Mode is enabled, the format of the tail tag changes. Specifically, a four

byte timestamp field is added between the payload and the tail tag as shown in Figure 4-6. PTP mode is enabled by

setting bit 6 in Global PTP Message Config 1 Register. Note that the KSZ8441/62/63 use a different method for passing

the timestamp between the switch and host.

In the switch-to-host direction, the switch sets the PTP Message Indication bit in the tail tag to indicate when the four-

byte receive timestamp is present. When PTP Message Indication is not set, the four-byte timestamp field is not present.

It is therefore essential for the host processor to read bit 7 of each tail tag in order to know the packet format.

The 32-bit timestamp consists of 2 bits for “seconds” and 30 bits for “nanoseconds”. The timestamp format is

(((second & 3) << 30) | nanosecond)

In the host-to-switch direction, the 4-byte timestamp field is always present when PTP is enabled, as shown in Figure 4-

6. This is true for all packets sent by the host, including IBA packets. The host uses this field to insert the receive time-

stamp from PTP Pdelay_Req messages into the Pdelay_Resp messages. For all other traffic and PTP message types,

the host should populate the timestamp field with zeros.

4.4.10

IGMP SUPPORT

For Internet Group Management Protocol (IGMP) support in Layer 2, the device provides two components:

• “IGMP” Snooping

• “Multicast Address Insertion” in the Static MAC Table

TABLE 4-14:

TRANSMIT TAIL TAG FORMAT (FROM HOST TO SWITCH)

Bits

Description

15:11

Reserved

Lookup

0 = Port forwarding is determined by tail tag bits [9:0] below.

1 = Tail tag bits [9:0] are ignored and port forwarding is determined by the standard

switch forwarding process (address lookup, VLAN, etc.)

Port Blocking Override

When set, packets will be sent from the specified port(s) regardless, and any port

blocking (see Port Transmit Enable in Port MSTP State Register) is ignored.

8:7

Egress priority (0 to 3)

Forward to Port 7

Forward to Port 6

Forward to Port 5

Forward to Port 4

Forward to Port 3

Forward to Port 2

Forward to Port 1

FIGURE 4-6:

PTP MODE TAIL TAG FRAME FORMAT

DEST

ADDRESS

SOURCE

ADDRESS

802.1Q

TAG

(4)

ETYPE or

LENGTH

TAIL

TAG

2 (From Host)

1 (To Host)

PAYLOAD

46 (42) - 1500

FCS

BYTES

TIME

STAMP

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