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KSZ9567RTXI-TR 数据表(PDF) 82 Page - Microchip Technology |
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KSZ9567RTXI-TR 数据表(HTML) 82 Page - Microchip Technology |
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82 / 232 page  KSZ9567R DS00002329D-page 82 2017-2019 Microchip Technology Inc. 5.1.4.8 Switch Maximum Transmit Unit Register 5.1.4.9 Switch ISP TPID Register 5.1.4.10 AVB Credit Based Shaper Strategy Register Address: 0x0308 - 0x0309 Size: 16 bits Bits Description Type Default 15:14 RESERVED R/W 00b 13:0 Maximum Frame Length (MTU) Specifies the maximum transmission unit (MTU), which is the maximum frame payload size. Frames which exceed this maximum are truncated. This value can be set as high as 9000 (= 0x2328) if jumbo frame support is required. Also refer to the Switch MAC Control 1 Register and Port MAC Control 0 Register. R/W 0x07D0 Address: 0x030A - 0x030B Size: 16 bits Bits Description Type Default 15:0 ISP Tag TPID Default tag TPID (EtherType) for untagged incoming frames or the ISP frame tag TPID for the double tagging function. R/W 0x9100 Address: 0x030E - 0x030F Size: 16 bits Bits Description Type Default 15:2 RESERVED RO 0x0000 1 Shaping Credit Accounting 1 = Shaper credit deduction occurs on both data and IPG + preamble 0 = Shaper credit deduction occurs on data only R/W 1b 0 Policing Credit Accounting 1 = Policing credit deduction occurs on both data and IPG + preamble 0 = Policing credit deduction occurs on data only R/W 1b |
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