KSZ9567RTXI-TR datasheet(138/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 138

 2017-2019 Microchip Technology Inc.

5.2.1.8

Port Status Register

Address:

0xN030

Port N: 1-7

Size:

8 bits

Bits

Description

Type

Default

7:5

RESERVED

000

4:3

Port Speed Status

For non-PHY ports, these bits duplicate the speed setting in the XMII Port

Control 1 Register bit 6 and XMII Port Control 0 Register bit 4.

For PHY ports, these bits indicate the actual link speed, which is also

available in the PHY Control Register.

00 = 10 Mb/s

01 = 100 Mb/s

10 = 1000 Mb/s

Port Duplex Status

For non-PHY ports, this bit duplicates the duplex setting in the XMII Port

Control 0 Register bit 6.

For PHY ports, this bit indicates the actual link duplex, which is also available

in the PHY Control Register.

1 = Full duplex

0 = Half duplex

1 or -

Transmit Flow Control Enabled Status

For non-PHY ports, this bit duplicates the Tx FC enable bit 5 in the XMII Port

Control 0 Register.

For PHY ports, this bit is set only when FC is enabled (PHY Auto-Negotiation

Advertisement Register, bits 11:10), link is up and FC is established via auto-

negotiation.

1 = TX flow control is enabled

0 = Disabled

Receive Flow Control Enabled Status

For non-PHY ports, this bit duplicates the Rx FC enable bit 3 in the XMII Port

Control 0 Register.

For PHY ports, this bit is set only when FC is enabled (PHY Auto-Negotiation

Advertisement Register, bits 11:10), link is up and FC is established via auto-

negotiation.

1 = RX flow control is enabled

0 = Disabled

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