P9415-R Datasheet

© 2021 Renesas Electronics Corporation

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May 4, 2021

9.6 LDO1P8 Capacitor

The P9415-R has an internal LDO regulator that must have at least a 1µF to 2.2µF capacitor connected from the LDO1P8 pin to PGND. This

capacitor should be as close as possible to the LDO1P8 pin with a close GND connection. A 0.1µF capacitor in a 0201 or 0402 size package

can be added for improved high-frequency decoupling of the LDO1P8 power rail because this voltage powers the internal ARM Cortex-M0

processor.

9.7 LDO5P0 Capacitor

The P9415-R has an internal LDO regulator that must have at least a 1µF to 2.2µF capacitor connected from the LDO5P0 pin to PGND. This

capacitor should be as close as possible to the LDO5P0 pin with a close PGND connection. A 0.1µF capacitor in a 0201 or 0402 size package

can be added for improved high-frequency decoupling of the LDO5P0 power rail because of this voltage powers the internal ADC and UVLO

circuits.

For additional power savings at higher input voltages, an external 5V supply should be connected to supply power to the P9415-R via the

LDO5P0 pin. The applied voltage to this pin must be > LDO5P0 regular output voltage to power the low-voltage circuitry from the external 5V

supply, while the external 5V supply should be between 5.2V to 5.5V.

9.8 PCLAMP Connection

The P9415-R has an internal automatic DC clamping feature to protect the device from events that cause high voltages to occur on the AC or

DC side of the rectifier. The clamping engages by the VRECT connection to the PCLAMP pin. The VRECT node must be connected to the

PCLAMP pin at all times during Rx mode operation. For greater than 5W operation, the VRECT node is connected to the PCLAMP pin using a

50Ω to 100Ω resistor with greater than 1/4W rating with 2.5x or greater over-power surge capability. For space-constrained designs, the

PCLAMP pin can be directly connected to the VRECT node for 5W or lower power operation.

Also, there is an option for external FET and resistor clamping by the use of the ECLAMP_DRV pin which can output 5V to drive the gate of

external MOSFET. This output is synchronized with the internal PCLAMP signal. ECLAMP_DRV can provide additional clamping capability as

needed and there is no thermal increase in the IC side because clamping energy is consumed in external components.

9.9 Transient Voltage Suppressors

The Transient Voltage Suppressor (TVS) is an active device that will direct high voltages from the input to ground, thus protecting the wireless

power device or other downstream ICs from being exposed to high voltages.

Transient Voltage Suppressor diodes should be added to the design from the AC1 and AC2 nodes to GND or from AC1 to AC2. These

components are useful to rapidly limit incoming ESD surges or situations when the TX incoming power exceeds the expected power and VRECT

voltage rises above target and Over-voltage protection threshold in less than 10µs to aid in voltage limiting the incoming AC waveforms in

conjunction with the PCLAMP power limiting circuitry.

A balance in Reverse Standoff Voltage (VRWM), Clamping Voltage (VCL), Break-down Voltage (VBR) relative to the expected Vrect operating

voltage Vrect (be sure minimum VBR is less than maximum operating Vrect value and that VCL is less than Vrect Absolute maximum voltage)

should be reached.

Table 6.

Transient Voltage Suppressors (TVS) Recommendations

VMLDO = 12V

D24V0L1B2LP

VRWM = 24V maximum

VBR = 26V minimum at 1mA

VCL = 42V maximum at 1A pp