P9415-R Datasheet

© 2021 Renesas Electronics Corporation

13

May 4, 2021

Symbol

Description

Conditions

Minimum

Typical

Maximum Units

VOH

Output High Voltage

IOH = 8mA (for all combined

GPIOs)

1.44

V

VOL

Output Low Voltage

IOL = 8mA (for all combined

GPIOs)

0.4

V

ECLAMP_DRV Output

VOH

Output High Voltage

IOH = -4mA

4.0

4.4

V

VOL

Output Low Voltage

IOL = 8mA

0.6

V

SCL, SDA (I2C Interfaces SCL (OD0), SDA (OD1)

fSCL

Clock Frequency

400

kHz

tHD,STA

Hold Time (Repeated) for

START Condition

0.6

µs

tHD:DAT

Data Hold Time

0

ns

tLOW

Clock Low Period

1.3

µs

tHIGH

Clock High Period

0.6

µs

tSU:STA

Set-up Time for Repeated

START Condition

0.6

µs

tBUF

Bus Free Time Between

STOP and START Condition

1.3

µs

CB

Capacitive Load for Each

Bus Line

150

pF

CI

SCL, SDA Input

Capacitance

5

pF

VIL

Input Threshold Low

0.7

V

VIH

Input Threshold High

1.4

V

ILKG

Input Leakage Current

V = 0V and 1.8V, pull-ups

disabled

-1

1

µA

VOL

Output Logic Low

IOL= 3mA

0.36

V

[a] VRECT may exceed 23.5V but the device EC table limits are not guaranteed under this condition.

[b] Input Voltage Operating Range is dependent upon the type of Transmitter Power Stage (full-bridge, half-bridge) and Transmitting Coil Inductance.

WPC Specifications should be consulted for appropriate input voltage ranges by end product type.

[c] Do not externally load. For internal biasing only.

[d] Full power transfer will not occur at the minimum IC operating specification.

[e] LDO1P8 pin can only be loaded as shown in reference schematics.

[f] Any open-drain GPIO pin (SCL, SDA, OD2, OD3, OD4) that is connected as an input to the ADC should stay below 2.1V to prevent saturation of

the ADC, and any push-pull GPIO pin (GP0, GP1, GP2, GP3, GP4, GP5, GP6) connected to the ADC, the voltage must be ≤ LDO1P8 to avoid

interference with the LDO1P8 power supply.