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P9415-R 数据表(PDF) 42 Page - Renesas Technology Corp |
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P9415-R 数据表(HTML) 42 Page - Renesas Technology Corp |
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42 / 62 page  P9415-R Datasheet © 2021 Renesas Electronics Corporation 42 May 4, 2021 Table 21. System Interrupt Clear Register (0x28, 0x29, 0x2A, 0x2B) in Rx Mode Address and Bit Register Field Name R/W Default Value Function and Description 0x2B [7:0] Reserved R/W 0 Reserved 0x2A [7] OVERCURRWARN R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x2A [6] ADTERROR R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x2A [5] ADTRCVD R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x2A [4] ADTSENT R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x2A [3] NTCOVERTEMP R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x2A [2] VRECTON R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x2A [1:0] Reserved R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [7] VSWITCHFAILED R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [6] SLEEPMODE R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [5] IDAUTHSUCCESS R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [4] IDAUTHFAILED R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [3] BCSUCCESS R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [2] BCTIMEOUT R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [1] TXAUTHSUCCESS R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x29 [0] TXAUTHFAILED R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x28 [7] LDODISABLE R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x28 [6] LDOENABLE R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x28 [5] MODECHHGED R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. 0x28 [4] TXDATARCVD R/W 0 AP writes 1 to clear the corresponding Interrupt Registers’ bit. This bit is self-cleared to 0 (by M0) afterward. |
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