P9415-R Datasheet

© 2021 Renesas Electronics Corporation

32

May 4, 2021

9.10GPIO Pins

The P9415-R has general-purpose input-output (GPIO) pins. The OD0-OD4 and GP0-GP6 pins are all multi-functional.OD0-OD4 pins have an

open-drained structure and GP0-GP6 pins have a push-pull structure.

9.10.1 OD0/SCL Pin

The OD0 pin has a digital function open-drain structure. It is assigned to SCL of the I2C function for the serial interface between the AP and the

P9415-R. An external pull-up register on the SCL line is required for I2C communication. OD0 can operate up to 5V.

9.10.2 OD1/SDA Pin

The OD1 pin is set as a digital function open-drain structure. It is assigned to the SDA function of the I2C serial interface bus between the AP

and the P9415-R. An external pull-up resistor on the SDA line is required for I2C communication. OD1 can operate up to 5V.

9.10.3 OD2/INT Pin

The OD2 pin is set as a digital function open-drain structure. It is assigned as the /INT signal for interrupt notification to the AP. /INT pin indicates

a major change of states or error modes such as over-current, over-voltage, or over-temperature event. Connect this pin to the AP I/O voltage

rail using an external pull-up resistor. The P9415-R drives this pin LOW to notify the AP of status changes.

9.10.4 OD3/ALIGN_X Pin and OD4/ALIGN_Y Pin

The XY alignment feature allows the P9415-R to sense its relative position to the Tx coil magnetic field center. When used, the XY alignment

coils should be connected to pins OD3(X-alignment coil input) and 0D4 (Y-alignment coil input). These signals are internally rectified, filtered,

and sensed through the ADC. The ADC values that represent Align X coil signal strength and Align Y coil signal strength can be read in 0x38

and 0x39 registers respectively.

Figure 23. Typical XY Align Coil Schematic Level Connection Guide

9.10.5 GP0/PWRGD Pin

The GP0 pin is a digital output referenced to LDO1P8. The AP can use the power good signal to turn on the charging connection indicator or

other system functions. Power good (PWRGD) pin is pulled low by default. In BPP mode, the power good pin is pulled high when MLDO is

enabled. In EPP mode, the power good pin is pulled high at the end of the negotiation phase by default. It can be configured to be pulled high

when MLDO Vout is enabled.

AlignY PCB coil

ALGX_OD3

10V/0402

1/16W/0402

1/16W/0402

LDO1P8

LDO1P8

R51 10k

ALGY

OPTIONAL :

XY Alignment

ALGY _OD4

R286

NP

R287

NP

10V/0402

1/16W/0402

R52 10k

AlignX PCB coil

ALGX

R280 0