STM32F103CBU6TR datasheet(115/116 Pages) STMICROELECTRONICS

115 / 116 page

DS5319 Rev 18

115/116

STM32F103x8, STM32F103xB

Revision history

115

05-Aug-2013

Updated the reference for ‘VESD(CDM)’ in Table 32: ESD absolute

maximum ratings

Corrected ‘tf(IO)out’ in Figure 30: I/O AC characteristics definition

Updated Table 52: UFQFPN48 mechanical data

21-Aug-2015

Updated Table 3: STM32F103xx family removing the note.

Updated Table 63: Ordering information scheme removing the note.

Updated Section 6: Package information and added Section : Marking of

engineering samples for all packages.

Updated I2C characteristics, added tSP parameter and note 4 in Table 40:

I2C characteristics.

Updated Figure 32: I2C bus AC waveforms and measurement circuit

swapping SCLL and SCLH.

Updated Figure 33: SPI timing diagram - slave mode and CPHA = 0.

Updated min/max value notes replacing ‘Guaranteed by design, not

tested in production” by “guaranteed by design”.

Updated min/max value notes replacing ‘based on characterization, not

tested in production” by “Guaranteed based on test during

characterization”.

Updated Table 19: Peripheral current consumption.

29-Mar-2022

Updated Table 5: Medium-density STM32F103xx pin definitions.

Updated Figure 37: ADC accuracy characteristics, Figure 38: Typical

connection diagram using the ADC and its footnotes.

Minor text edits across the whole document.

Table 63. Document revision history (continued)

Date

Revision

Changes

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