STM32U535NET3QTR datasheet(49/278 Pages) STMICROELECTRONICS

49 / 278 page

DS14217 Rev 1

49/278

STM32U535xx

Functional overview

3.14.1

LPGPIO TrustZone security

Each I/O pin registers bit of the LPGPIO is configured as secure if the corresponding I/O is

configured as secure in the GPIO.

3.15

Multi-AHB bus matrix

A 32-bit multi-AHB bus matrix interconnects all master (CPU, GPDMA1, SDMMC1) and

slave (flash memory, RAM, OCTOSPI, SRAMs, AHB and APB) peripherals. It also ensures

a seamless and efficient operation even when several high-speed peripherals work

simultaneously.

Another multi-AHB bus matrix interconnects two masters (previous AHB bus matrix slave

port and LPDMA1) and all slaves that are functional in Stop 2 modes (SRAM4 and

AHB/APB peripherals functional in Stop 2 mode).

3.16

System configuration controller (SYSCFG)

The STM32U535xx devices feature a set of configuration registers. The main purposes of

the system configuration controller are the following:

•

Managing robustness feature

•

Configuring FPU interrupts

•

Enabling/disabling the FMP high-drive mode of some I/Os and voltage booster for I/Os

analog switches

•

Managing the I/O compensation cell

•

Configuring register security access

3.17

General purpose direct memory access controller (GPDMA)

The general purpose direct memory access (GPDMA) controller is a bus master and system

peripheral.

The GPDMA is used to perform programmable data transfers between memory-mapped

peripherals and/or memories via linked-lists, upon the control of an off-loaded CPU.

The GPDMA main features are:

•

Dual bidirectional AHB master

•

Memory-mapped data transfers from a source to a destination:

–

Peripheral-to-memory

–

Memory-to-peripheral

–

Memory-to-memory

–

Peripheral-to-peripheral

•

Autonomous data transfers during Sleep and Stop modes

•

Transfers arbitration based on a four-grade programmed priority at a channel level:

–

One high-priority traffic class, for time-sensitive channels (queue 3)

–

Three low-priority traffic classes, with a weighted round-robin allocation for non

time-sensitive channels (queues 0, 1, 2)

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