STM32U535NET3QTR datasheet(59/278 Pages) STMICROELECTRONICS

59 / 278 page

DS14217 Rev 1

59/278

STM32U535xx

Functional overview

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Data alignment with built-in data coherency

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DMA support

•

Low-power

–

HCLK frequency reduced for low-power operation while still keeping optimum

ADC performance

–

Wait mode: ADC overrun prevented in applications with low frequency HCLK

–

Auto-off mode: ADC automatically powered off except during the active

conversion phase, dramatically reducing the ADC power consumption

–

Autonomous mode: In low-power modes down to Stop 2 mode, the ADC4 is

automatically switched on when a trigger occurs to start conversion, and it is

automatically switched off after conversion. Data are transfered in SRAM

with DMA.

–

ADC4 interrupts wake up the device from Stop 0, Stop 1 and Stop 2 modes.

•

Analog input channels

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Up to 19 external analog inputs

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One channel for the internal temperature sensor (VSENSE)

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One channel for the internal reference voltage (VREFINT)

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One channel for the internal digital core voltage (VCORE)

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One channel for monitoring the external VBAT power supply pin

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Connection to two DAC internal channels

•

Start-of-conversion can be initiated:

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By software

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By hardware triggers with configurable polarity (timer events or GPIO input

events)

•

Conversion modes

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Conversion of a single channel or scan of a sequence of channels

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Selected inputs converted once per trigger in Single mode

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Selected inputs converted continuously in Continuous mode

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Discontinuous mode

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Interrupt generation at the end of sampling, end of conversion, end of sequence

conversion, and in case of analog watchdog or overrun events, with wake-up from Stop

capability

•

Analog watchdog

•

Oversampler

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16-bit data register

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Oversampling ratio adjustable from 2 to 256

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Programmable data shift up to 8 bits

•

ADC supply requirements: 1.62 to 3.6 V

•

ADC input range: VSSA < VIN < VREF+

Note:

The ADC4 analog block clock frequency must be between 140 kHz and 55 MHz.

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