STM32U535NET3QTR datasheet(53/278 Pages) STMICROELECTRONICS

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DS14217 Rev 1

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STM32U535xx

Functional overview

3.19

Interrupts and events

3.19.1

Nested vectored interrupt controller (NVIC)

The devices embed a NVIC that is able to manage 16 priority levels and to handle up to 114

maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.

The NVIC benefits are the following:

•

closely coupled NVIC giving low-latency interrupt processing

•

interrupt entry vector table address passed directly to the core

•

early processing of interrupts

•

processing of late arriving higher priority interrupts

•

support for tail chaining

•

processor state automatically saved

•

interrupt entry restored on interrupt exit with no instruction overhead

•

TrustZone support: NVIC registers banked across secure and nonsecure states

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.19.2

Extended interrupt/event controller (EXTI)

The EXTI manages the individual CPU and system wake-up through configurable event

inputs. It provides wake-up requests to the power control, and generates an interrupt

request to the CPU NVIC and events to the CPU event input. For the CPU an additional

event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can also be used in Run modes.

The EXTI also includes the EXTI multiplexer I/O port selection.

The EXTI main features are the following:

•

All event inputs allowed to wake up the system

•

Configurable events (signals from I/Os or peripherals able to generate a pulse)

–

Selectable active trigger edge

–

Interrupt pending status register bit independent for the rising and falling edge

–

Individual interrupt and event generation mask, used for conditioning the CPU

wake-up, interrupt and event generation

–

Software trigger possibility

•

TrustZone secure events

–

The access to control and configuration bits of secure input events can be made

secure

•

EXTI I/O port selection

Table 14. LPDMA1 autonomous mode and wake-up in low-power modes

Feature

Low-power modes

Autonomous mode and wake-up

LPDMA1 in Sleep, Stop 0, Stop 1 and Stop 2 modes

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