STM32U535NET3QTR datasheet(34/278 Pages) STMICROELECTRONICS

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Functional overview

STM32U535xx

34/278

DS14217 Rev 1

Figure 3. STM32U535xx power supply overview (without SMPS)

In this document, VDDIOx (with x = 1 or 2) refers to the I/O power supply. VDDIO1 is supplied

by VDD. VDDIO2 is the independent power supply for PG[15:2].

During power-up and power-down phases, the following power sequence requirements

must be respected:

•

When VDD is below 1 V, other power supplies (VDDA, VDDIO2, VDDUSB) must remain

below VDD + 300 mV.

•

When VDD is above 1 V, all power supplies are independent.

•

During the power-down phase, VDD can temporarily become lower than other supplies

only if the energy provided to the MCU remains below 1 mJ. This allows external

decoupling capacitors to be discharged with different time constants during the

power-down transient phase.

MSv70512V2

USB transceiver

Core

SRAM1

SRAM2

SRAM4

Digital

peripherals

VDDA domain

Standby circuitry

(Wakeup logic, IWDG)

Low-voltage detector

LDO regulator

I/O ring

VCORE domain

Flash memory

VDDUSB

VDDIO2

VDDIO1

I/O ring

PG[15:2]

VDDIO2

VDDA

VSSA

VSS

VDDIO2 domain

VDD domain

VCORE

VSS

VDD

VBAT

VCAP

A/D converters

Comparators

D/A converters

Operational amplifiers

Voltage reference buffer

Temperature sensor

Reset block

3 x PLL

Internal RC oscillators

LSE crystal 32 kHz oscillator

LSI 32 kHz oscillator

Backup registers

RCC_BDCR and PWR_BDCR1 registers

RTC

TAMP

BKPSRAM

Backup domain

STM32U535NET3QTR 数据表(PDF) 34 Page - STMicroelectronics

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