STM32U535NET3QTR datasheet(80/278 Pages) STMICROELECTRONICS

80 / 278 page

Functional overview

STM32U535xx

80/278

DS14217 Rev 1

•

Programmable number of data within a transaction to control SS and CRC

•

Dedicated transmission and reception flags with interrupt capability

•

SPI Motorola® and Texas Instruments® formats support

•

Hardware CRC feature can secure communication at the end of transaction by:

–

Adding CRC value in Tx mode

–

Automatic CRC error checking for Rx mode

•

Error detection with interrupt capability in case of data overrun, CRC error, data

underrun at slave, mode fault at master

•

Two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability

•

Programmable number of data in transaction

•

Configurable FIFO thresholds (data packing)

•

Configurable behavior at slave underrun condition (support of cascaded circular

buffers)

•

Autonomous functionality in Stop modes (handling of the transaction flow and required

clock distribution) with wake-up from stop capability

•

Optional status pin RDY signalizing the slave device ready to handle the data flow.

3.41

Serial audio interfaces (SAI)

The devices embed one SAI. Refer to Table 23: SAI implementation for the features

implementation. The SAI bus interface handles communications between the

microcontroller and the serial audio protocol.

The SAI peripheral supports:

•

Two independent audio sub-blocks that can be transmitters or receivers with their

respective FIFO

•

8-word integrated FIFOs for each audio sub-block

•

Synchronous or Asynchronous mode between the audio sub-blocks

•

Master or slave configuration independent for both audio sub-blocks

•

Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode

Table 22. SPI features

SPI feature

SPI1, SPI2

(full feature set instances)

SPI3

(limited feature set instance)

Data size

Configurable from 4 to 32-bit

8/16-bit

CRC computation

CRC polynomial length

configurable from 5 to 33-bit

CRC polynomial length

configurable from 9 to 17-bit

Size of FIFOs

16x 8-bit

8x 8-bit

Number of transfered data

Unlimited, expandable

Up to 1024, no data counter

Autonomous in Stop 0, Stop 1 mode

with wake-up capability

Yes

Autonomous in Stop 2 mode with

wake-up capability

Yes

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