STM32U535NET3QTR datasheet(236/278 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32U535xx

236/278

DS14217 Rev 1

5.3.28

ADF/MDF characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature, fAHB frequency and VDD supply voltage

conditions summarized in Table 32, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics.

Table 116. ADF characteristics(1)

Symbol

Parameter

Conditions

Min

Typ Max Unit

fCCKI

Input clock frequency via

ADF_CCK[1:0] pin, in SLAVE

SPI mode

1.71 ≤ VDD ≤ 3.6 V

MHz

fCCKO

Output clock frequency in

MASTER SPI mode

fCCKOLF

Output clock frequency in

LF_MASTER SPI mode

fSYMB

Input symbol rate in

Manchester mode

tHCCKI

tLCCKI

ADF_CCK[1:0] input clock

high and low time

In SLAVE SPI mode

2 ×

Tadf_proc_ck(2)

tHCCKO

tLCCKO

ADF_CCK[1:0] output clock

high and low time

In MASTER SPI mode

2 ×

Tadf_proc_ck

tHCCKOLF

tLCCKOLF

ADF_CCK[1:0] output clock

high and low time

In LF_MASTER SPI mode

Tadf_proc_ck

tSUCCKI

Data setup time with respect

to ADF_CCK[1:0] input

In SLAVE SPI mode:

ADF_CCK[1:0] configured in

input, measured on rising and

falling edge

4.5

tHDCCKI

Data hold time with respect to

ADF_CCK[1:0] input

tSUCCKO

Data setup time with respect

to ADF_CCK[1:0] output

In MASTER SPI mode:

ADF_CCK[1:0] configured in

output, measured on rising and

falling edge

5.5

tHDCCKO

Data hold time with respect to

ADF_CCK[1:0] output

tSUCCKOLF

Data setup time with respect

to ADF_CCK[1:0] output

In LF_MASTER SPI mode:

ADF_CCK[1:0] configured in

output, measured on rising and

falling edge

19.5

tHDCCKOLF

Data hold time with respect to

ADF_CCK[1:0] output

1. Evaluated by characterization. Not tested in production.

2. Tadf_proc_ck is the period of the ADF processing clock.

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