4

Connecting to the SPI bus

All instructions, addresses, and input data bytes are shifted in to the device, the most significant bit first. The

serial data input (D) is sampled on the first rising edge of the serial clock (C) after chip select (S) goes low.

All output data bytes are shifted out of the device, the most significant bit first. The serial data output (Q) is

latched on the first falling edge of the serial clock (C) after the instruction (such as the read from memory array

and read status register instructions) have been clocked into the device.

Figure 5. Bus master and memory devices on the SPI bus

AI12836b

SPI Bus Master

SDO

SDI

SCK

C

Q

D

C

Q

D

SPI Memory

Device

C

Q

D

CS3

CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

W

W

HOLD

W

R

R

R

R

SPI Memory

Device

SPI Memory

Device

VCC

VCC

VSS

VSS

VSS

VCC

S

S

S

HOLD

HOLD

VCC

VSS

1.

The write protect (W) and hold (HOLD) signals should be driven, high, or low as appropriate.

Figure 5 shows an example of three memory devices connected to an SPI bus master. Only one memory device

is selected at a given time, so only one memory device drives the serial data output (Q) line at that time. The

other memory devices are in high impedance state.

The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the bus master leaves the

S line in the high impedance state.

In applications where the bus master may leave all SPI bus lines in high impedance at the same time (for

example, if the bus master is reset during the transmission of an instruction), it is recommended to connect the

clock line (C) to an external pull-down resistor so that, if all inputs/outputs become high impedance, the C line is

pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and

so, that the tSHCH requirement is met. The typical value of R is 100 kΩ.

M95M02-DR M95M02-DF

Connecting to the SPI bus

DS7024 - Rev 13

page 6/45