The protection features of the device are summarized in Table 6.

When the status register write disable (SRWD) bit in the status register is 0 (its initial delivery state), it is possible

to write to the status register (provided that the WEL bit has previously been set by a WREN instruction),

regardless of the logic level applied on the write protect (W) input pin.

When the status register write disable (SRWD) bit in the Status register is set to 1, two cases should be

considered, depending on the state of the write protect (W) input pin:

•

If write protect (W) is driven high, it is possible to write to the status register (provided that the WEL bit has

previously been set by a WREN instruction).

•

If write protect (W) is driven low, it is not possible to write to the status register even if the WEL bit has

previously been set by a WREN instruction. (attempts to write to the status register are rejected, and are

not accepted for execution). As a consequence, all the data bytes in the memory area, which are software-

protected (SPM) by the block protect (BP1, BP0) bits in the status register, are also hardware-protected

against data modification.

Regardless of the order of the two events, the hardware-protected mode (HPM) can be entered by:

•

either setting the SRWD bit after driving the write protect (W) input pin low,

•

or driving the write protect (W) input pin low after setting the SRWD bit.

Once the hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the write

protect (W) input pin.

If the write protect (W) input pin is permanently tied high, the hardware-protected mode (HPM) can never be

activated, and only the software-protected mode (SPM), using the block protect (BP1, BP0) bits in the status

register, can be used.

M95M02-DR M95M02-DF

Write status register (WRSR)

DS7024 - Rev 13

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