7

Power-up and delivery state

7.1

Power-up state

After power-up, the device is in the following state:

•

standby power mode

•

deselected (after power-up, a falling edge is required on chip select (S) before any instructions can be

started)

•

not in the hold condition

•

the write enable latch (WEL) is reset to 0

•

write in progress (WIP) is reset to 0.

The SRWD, BP1 and BP0 bits of the status register are unchanged from the previous power-down (they are

non-volatile bits).

7.2

Initial delivery state

The device is delivered with the memory array and identification page bits set to all 1s (each byte = FFh). The

status register write disable (SRWD) and block protect (BP1 and BP0) bits are initialized to 0.

M95M02-DR M95M02-DF

Power-up and delivery state

DS7024 - Rev 13

page 26/45