6.4

Write status register (WRSR)

The write dtatus register (WRSR) instruction is used to write new values to the status register. Before it can be

accepted, a write enable (WREN) instruction must have been previously executed.

The write Status register (WRSR) instruction is entered by driving chip select (S) low, followed by the instruction

code, the data byte on serial data input (D) and chip select (S) driven high. Chip select (S) must be driven high

after the rising edge of serial clock (C) that latches in the eighth bit of the data byte, and before the next rising

edge of serial clock (C). Otherwise, the write status register (WRSR) instruction is not executed.

The instruction sequence is shown in Figure 12.

Figure 12. Write status register (WRSR) sequence

C

D

S

2

1

3

4

5

6

7

8

9 10

11 12 13 14 15

Instruction

0

MS47556V1

Q

Status Register In

High impedance

MSB

7

6

5

4

3

2

1

0

Driving the chip select (S) signal high at a byte boundary of the input data triggers the self-timed write cycle that

takes tW to complete (as specified in AC tables in Section 9 DC and AC parameters).

While the write status register cycle is in progress, the status register may still be read to check the value of the

write in progress (WIP) bit: the WIP bit is 1 during the self-timed write cycle tW, and 0 when the write cycle is

complete. The WEL bit (Write enable latch) is also reset at the end of the write cycle tW.

The write status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD

bits:

•

The block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in

Table 3. Write-protected block size.

•

The SRWD (status register write disable) bit, in accordance with the signal read on the write protect pin

(W), enables the user to set or reset the write protection mode of the status register itself, as defined in

Table 6. When in write-protected mode, the write status register (WRSR) instruction is not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including

the tW write cycle.

The write status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the status register. Bits

b6, b5, b4 are always read as 0.

Table 6. Protection modes

W

signal

SRWD

bit

Mode

Write protection of the Status register

Memory content

Protected area(1) Unprotected area(1)

1

0

Software-

protected

(SPM)

Status register is writable (if the WREN

instruction has set the WEL bit).

The values in the BP1 and BP0 bits can be

changed.

Write

‑protected

Ready to accept

write instructions

0

0

1

1

0

1

Hardware-

protected

(HPM)

Status register is hardware write-protected.

The values in the BP1 and BP0 bits cannot

be changed.

Write

‑protected

Ready to accept

write instructions

1. As defined by the values in the Block protect (BP1, BP0) bits of the Status register. See Table 3. Write-protected block size.

M95M02-DR M95M02-DF

Write status register (WRSR)

DS7024 - Rev 13

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