6.6.1

Cycling with error correction code (ECC x4)

M95M02-D devices offer an error correction code (ECC), an internal logic function transparent for the SPI

communication protocol.

The ECC logic is implemented on each group of four EEPROM bytes. (A group of four bytes is located at

addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes

happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value.

The read reliability is therefore much improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.

In this case, the ECC function also writes/cycles the three other bytes located in the same group. As a

consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over

the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must

remain below the maximum value defined in Table 11. Cycling performance by groups of four bytes.

M95M02-DR M95M02-DF

Write to memory array (WRITE)

DS7024 - Rev 13

page 21/45