5.4

Status register

The status register contains a number of status and control bits that can be read or set (as appropriate) by

specific instructions. See Section 6.3 Read status register (RDSR) for a detailed description of the status register

bits.

5.5

Data protection and protocol control

The device features the following data protection mechanisms:

•

Before accepting the execution of the write and write status register instructions, the device checks

whether the number of clock pulses comprised in the instructions is a multiple of eight.

•

All instructions that modify data must be preceded by a write enable (WREN) instruction to set the write

enable latch (WEL) bit.

•

The block protect (BP1, BP0) bits in the status register are used to configure part of the memory as

read-only.

•

The write protect (W) signal is used to protect the block protect (BP1, BP0) bits in the status register.

For any instruction to be accepted, and executed, chip select (S) must be driven high after the rising edge of

serial clock (C) for the last bit of the instruction, and before the next rising edge of serial clock (C).

Two points to note in the previous sentence:

•

The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth bit of a data byte,

depending on the instruction (except for read status register (RDSR) and read (READ) instructions).

•

The “next rising edge of serial clock (C)” might (or might not) be the next bus transaction for some other

device on the SPI bus.

Table 3. Write-protected block size

Status register bits

Protected block

Protected array addresses

BP1

BP0

0

0

None

None

0

1

Upper quarter

30000h - 3FFFFh

1

0

Upper half

20000h - 3FFFFh

1

1

Whole memory

00000h - 3FFFFh

M95M02-DR M95M02-DF

Status register

DS7024 - Rev 13

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