6

Instructions

Each command is composed of bytes (MSB bit transmitted first), initiated with the instruction byte, as summarized

in Table 4.

If an invalid instruction is sent (one not contained in Table 4), the device automatically enters in a wait state until

deselected.

Table 4. Instruction set

Instruction

Description

Instruction format

WREN

Write enable

0000 0110

WRDI

Write disable

0000 0100

RDSR

Read status register

0000 0101

WRSR

Write status register

0000 0001

READ

Read from memory array

0000 0011

WRITE

Write to memory array

0000 0010

RDID

Read identification page

1000 0011

WRID

Write identification page

1000 0010

RDLS

Read identification page lock status

1000 0011

LID

Lock identification page in read-only mode

1000 0010

For read and write commands to the memory array and identification page the address is defined by three bytes

as explained in Table 5.

Table 5. Significant bits within the address bytes

Instruction(1)(2)

Upper address byte

Middle address byte

Lower address byte

b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

READ

or WRITE

X

X

X

X

X

X

A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

RDID

or WRID

X

X

X

X

X

X

X

X

X

X

X

X

X

0

X

X A7 A6 A5 A4 A3 A2 A1 A0

RDLS

or LID

X

X

X

X

X

X

X

X

X

X

X

X

X

1

X

X

X

X

X

X

X

X

X

X

1. A: Significant address bit

2. X: Don't Care bit

M95M02-DR M95M02-DF

Instructions

DS7024 - Rev 13

page 11/45