ADV7393 datasheet(45/96 Pages) AD

45 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 45 of 96

FEATURES

OUTPUT OVERSAMPLING

The ADV739x include an on-chip phase-locked loop (PLL) that

allows for oversampling of SD, ED, and HD video data. By

default, the PLL is disabled. The PLL can be enabled using

Subaddress 0x00, Bit 1 = 0.

Table 35 shows the various oversampling rates supported in the

ADV739x.

ED/HD NONSTANDARD TIMING MODE

Subaddress 0x30, Bits[7:3] = 00001

For any ED/HD input data that does not conform to

the standards listed in the ED/HD input mode table

(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard

timing mode can be used to interface to the ADV739x.

ED/HD nonstandard timing mode can be enabled by

setting Subaddress 0x30, Bits[7:3] to 00001.

A clock signal must be provided on the CLKIN pin. HSYNC

and VSYNC must be toggled by the user to generate the

appropriate horizontal and vertical synchronization pulses on

the analog output from the encoder. Figure 61 illustrates the

various output levels that can be generated. Table 36 lists the

transitions required to generate the various output levels.

Embedded EAV/SAV timing codes are not supported in

ED/HD nonstandard timing mode.

The user must ensure that appropriate pixel data is applied to

the encoder where the blanking level is expected at the output.

Macrovision (ADV7390/ADV7392 only) and output

oversampling are not available in ED/HD nonstandard timing

mode. The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in

ED/HD nonstandard timing mode.

ACTIVE VIDEO

ANALOG

OUTPUT

a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.

b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.

c = SYNCHRONIZATION PULSE LEVEL.

BLANKING LEVEL

Figure 61. ED/HD Nonstandard Timing Mode Output Levels

Table 35. Output Oversampling Modes and Rates

Input Mode

(0x01, Bits[6:4])

PLL and Oversampling

Control (0x00, Bit 1)

SD/ED Oversample Rate

Select (0x0D, Bit 3)

HD Oversample Rate

Select (0x31, Bit 1)

Oversampling Mode

and Rate

000

SD (2×)

000

SD (8×)

000

SD (16×)

001/010

ED (1×)

001/010

ED (4×)

001/010

ED (8×)

001/010

HD (1×)

001/010

HD (2×)

001/010

HD (4×)

111

ED (at 54 MHz)

ED (@ 54 MHz) (1×)

111

ED (at 54 MHz)

ED (@ 54 MHz) (4×)

111

ED (at 54 MHz)

ED (@ 54 MHz) (8×)

Table 36. ED/HD Nonstandard Timing Mode Synchronization Signal Generation

Output Level Transition1

HSYNC

VSYNC

→ c

→ 0

→ 0 or 02

→ a

→ 1

→ b

→ 1

→ b

→ 1

1 a = Tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 61.

2 If VSYNC = 1, it should transition to 0. If VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, VSYNC should always be 0.

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