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ADV7393 数据表(PDF) 86 Page - Analog Devices |
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ADV7393 数据表(HTML) 86 Page - Analog Devices |
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86 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 86 of 96 Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x88 0x10 10-bit input enabled. Table 68. 10-Bit 525i YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x88 0x10 10-bit input enabled. 0x8A 0x0C Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. Table 69. 16-Bit 525i YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. pedestal enabled. 0x88 0x08 16-bit input enabled. 0x8A 0x0C Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. Table 70. 16-Bit 525i YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x88 0x08 16-bit input enabled. 0x8A 0x0C Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. Table 71. 16-Bit 525i RGB In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x87 0x80 RGB input enabled. 0x88 0x08 16-bit input enabled. 0x8A 0x0C Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. Table 72. 16-Bit 525i RGB In, CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xCB Pixel data valid. CVBS/S-Video out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x87 0x80 RGB input enabled. 0x88 0x08 16-bit input enabled. 0x8A 0x0C Timing Mode 2 (Slave). HSYNC/VSYNC synchronization. |
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