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ADV7393 数据表(PDF) 74 Page - Analog Devices

部件名 ADV7393
功能描述  Low Power, Chip Scale 10-Bit SD/HD Video Encoder
PDF  96 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7393 数据表(HTML) 74 Page - Analog Devices

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ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 74 of 96
622
623
624
625
21
22
23
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
FIELD
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
VERTICAL BLANK
ODD FIELD
EVEN FIELD
DISPLAY
320
FIELD
5
7
6
4
3
2
1
HSYNC
HSYNC
Figure 107. SD Timing Mode 1, Slave Option, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624.
Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the HSYNC and
VSYNC pins, respectively.
FIELD
PIXEL
DATA
Cb
Y
Cr
Y
HSYNC
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 108. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the HSYNC and VSYNC
pins, respectively.



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