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数据搜索系统，热门电子元器件搜索 |
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ADV7393 数据表(PDF) 13 Page - Analog Devices |
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ADV7393 数据表(HTML) 13 Page - Analog Devices |
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13 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 13 of 96 Y0 Y1 Y2 Y3 a Cr2 Cb2 Cr0 Cb0 b Y OUTPUT HSYNC VSYNC a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. PIXEL PORT PIXEL PORT Figure 12. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram PIXEL PORT Cb0 Y0 Cr0 Y1 a HSYNC VSYNC b Y OUTPUT a = AS PER RELEVANT STANDARD. b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 13. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram |
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