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ADV7393 数据表(PDF) 73 Page - Analog Devices |
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ADV7393 数据表(HTML) 73 Page - Analog Devices |
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73 / 96 page ![]() ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 73 of 96 622 623 624 625 21 22 23 DISPLAY DISPLAY VERTICAL BLANK H F ODD FIELD EVEN FIELD 309 310 311 312 314 315 316 317 318 319 320 334 335 336 DISPLAY DISPLAY VERTICAL BLANK H F ODD FIELD EVEN FIELD 313 7 6 5 4 3 2 1 Figure 104. SD Timing Mode 0, Master Option, PAL ANALOG VIDEO H F Figure 105. SD Timing Mode 0, Master Option, Data Transitions Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0) In this mode, the ADV739x accepts horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as per CCIR-624. HSYNC and FIELD are input on the HSYNC and VSYNC pins, respectively. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK 522 523 524 525 59 10 11 20 21 22 DISPLAY DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD FIELD FIELD HSYNC HSYNC 7 6 4 3 2 1 8 Figure 106. SD Timing Mode 1,Slave Option, NTSC |
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