ADV7393 datasheet(46/96 Pages) AD

46 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 46 of 96

ED/HD TIMING RESET

Subaddress 0x34, Bit 0

An ED/HD timing reset is achieved by setting the ED/HD

timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this

state, the horizontal and vertical counters remain reset. When

this bit is set back to 0, the internal counters resume counting.

This timing reset applies to the ED/HD timing counters only.

SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER

RESET, AND TIMING RESET

Subaddress 0x84, Bits[2:1]

Together with the SFL/MISO pin and SD Mode Register 4

(Subaddress 0x84, Bits[2:1]), the ADV739x can be used in

timing reset mode, subcarrier phase reset mode, or SFL mode.

•

In timing reset (TR) mode (Subaddress 0x84, Bits[2:1] = 10),

a timing reset is achieved in a low-to-high transition on the

SFL/MISO pin. In this state, the horizontal and vertical

counters remain reset. Upon releasing this pin (set to low),

the internal counters resume counting, starting with Field 1,

and the subcarrier phase is reset.

The minimum time the pin must be held high is one clock

cycle; otherwise, this reset signal may not be recognized.

This timing reset applies to the SD timing counters only.

•

In subcarrier reset (SCR) mode (Subaddress 0x84, Bits[2:1]

= 01), a low-to-high transition on the SFL/MISO pin resets

the subcarrier phase to 0 on the field following the

subcarrier phase reset.

This reset signal must be held high for a minimum of one

clock cycle.

Because the field counter is not reset, it is recommended to

apply the reset signal in Field 7 (PAL) or Field 3 (NTSC).

The reset of the phase then occurs on the next field, that is,

Field 1, which is lined up correctly with the internal

counters. The field count register at Subaddress 0xBB can

be used to identify the number of the active field.

•

In subcarrier frequency lock (SFL) mode (Subaddress 0x84,

Bits[2:1] = 11), the ADV739x can be used to lock to an

external video source. The SFL mode allows the ADV739x

to automatically alter the subcarrier frequency to compensate

for line length variations. When the part is connected to a

device such as an ADV7403 video decoder that outputs a

digital data stream in the SFL format, the part automatically

changes to the compensated subcarrier frequency on a

line-by-line basis (see Figure 64). This digital data stream is

67 bits wide and the subcarrier is contained in Bit 0 to Bit

21. Each bit is two clock cycles long.

DISPLAY

NO TIMING RESET APPLIED

TIMING RESET APPLIED

START OF FIELD 4 OR 8

FSC PHASE = FIELD 4 OR 8

FSC PHASE = FIELD 1

TIMING RESET PULSE

307

310

307

345

313

320

DISPLAY

START OF FIELD 1

Figure 62. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 10)

NO FSC RESET APPLIED

FSC PHASE = FIELD 4 OR 8

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

FSC RESET APPLIED

FSC RESET PULSE

FSC PHASE = FIELD 1

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

Figure 63. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)

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