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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 124 of 140

When this bit is set to logic one, the SS pin is defined as the Slave Select input pin

for the SPI slave interface

0xEA

Receive buffer overflow write enable

If the SPIRX SFR has not been read when a new data byte is

received, the new byte will be discarded.

RxOFW

If the SPIRX SFR has not been read when a new data byte is

received, the new byte will overwrite the old data.

1-0

0xE9 –

0xE8

SPIR[1:0]

Master Mode: SPI SCLK frequency

[1:0]

Fcore / 8 = 512kHz if Fcore = 4.096MHz

Fcore / 16 = 256kHz if Fcore = 4.096MHz

Fcore / 32 = 128kHz if Fcore = 4.096MHz

Fcore / 64 = 64kHz if Fcore = 4.096MHz

Table 125. SPI Configuration Register SFR (SPIMOD2, 0xE9)

Bit

Location

Bit

Mnemonic

Default

Value

Description

Master Mode: SPI continuous transfer mode enable bit

The SPI interface will stop after one byte is transferred and SS will

be deasserted. A new data transfer can be intiated after a stalled

period.

SPICONT

The SPI interface will continue transferring data until no valid data is

availbale in the SPITx SFR. SS will remain asserted until SPITx SFR

and the transmit shift register is empty.

SPI interface enable bit

The SPI interface is disabled.

SPIEN

The SPI interface is enabled

SPI Open Drain Outputs configuration bit

Internal pull-up resistors are connected to the SPI outputs

SPIODO

The SPI outputs are open-drain and need external pull-up resistors

SPI Master Mode enable bit

The SPI interface is defined as a Slave

SPIMS_b

The SPI interface is defined as a Master

SPI clock polarity configuration bit – see Figure 84.

The default state of SCLK is low and the first SCLK edge is rising.

Depending on SPICPHA bit, the SPI data output changes state on

the falling or rising edge of SCLK while the SPI data input is sampled

on the rising or falling edge of SCLK.

SPICPOL

The default state of SCLK is high and the first SCLK edge is falling.

Depending on SPICPHA bit, the SPI data output changes state on

the rising or falling edge of SCLK while the SPI data input is sampled

on the falling or rising edge of SCLK.

SPI clock phase configuration bit – see Figure 84.

The SPI data output changes state when SS goes low, at the second

edge of SCLK and then every two subsequent edges while the SPI

data input is sampled at the first SCLK edge and then every two

subsequent edges.

SPICPHA

The SPI data output changes state at the first edge of SCLK and then

every two subsequent edges while the SPI data input is sampled at

the second SCLK edge and then every two subsequent edges.

SPILSBF

Master Mode: LSB first configuration bit

ADE7169F16 数据表(PDF) 124 Page - Analog Devices

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