ADE7169F16 datasheet(125/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 125 of 140

The MSB of the SPI outputs is transmitted first

The LSB of the SPI outputs is transmitted first

Transfer and interrupt mode of the SPI interface.

Transfer is initiated when data is read from SPIRx SFR and an interrupt is

generated when there is new data in the SPIRx SFR.

TIMODE

Transfer is initiated when data is written to the SPITx SFR and an

interrupt is generated when the SPITx SFR is empty.

Table 126. SPI Interrupt Status Register SFR (SPISTAT, 0xEA)

Bit

Location

Interrupt Flag

Default

Value

Description

SPI Peripheral Busy Flag

The SPI peripheral is idle

BUSY

The SPI peripheral is busy transferring data in slave or master mode.

SPI Multi-Master Error Flag

A multiple master error has not occurred.

MMERR

If the SS_EN bit is set, enabling the Slave Select input and the SS is asserted

while the SPI peripheral is transferring data as a master, then this flag is raised

to indicate the error.

SPI Receive Overflow Error Flag.

Reading the SPIRx SFR will clear this bit.

SPIR

xOF

TIMODE

The SPIRX register contains valid data

SPIRxOF

This bit is set if the SPIRX register is not read before the end of the

next byte transfer. If the RxOF_EN bit is set and this condition

occurs, SPIRX will be overwritten.

SPI Receive Mode Interrupt Flag.

Reading the SPIRx SFR will clear this bit.

SPIRxI

TIMODE

The SPIRX register does not contain new data.

This bit is set when the SPIRX register contains new data. If the

SPI/I2C interrupt is enabled, an interrupt will be generated when

this bit is set. If the SPIRX register isn’t read before the end of the

current byte transfer, the transfer will stop and the SS will be

deasserted.

SPIRxIRQ

The SPIRX register contains new data.

SPIRxBF

Status bit for SPI Rx buffer. When set the Rx FIFO is full. A read of the SPIRx will clear this

flag

SPITxUF

Status bit for SPI Tx buffer. When set the Tx FIFO is underflowing and data can be write

into SPITx. A read of the SPISTAT SFR or a write to the SPITx SFR will clear this flag.

SPI Transmit Mode Interrupt Flag.

Writing new data to the SPITx SFR will clear this bit.

SPITxIRQ

TIMODE

The SPITX register is full.

The SPITX register is empty.

SPITxIRQ

This bit is set when the SPITX register is empty. If the SPI/I2C

interrupt is enabled, an interrupt will be generated when

this bit is set. If new data isn’t written into the SPITX SFR

before the end of the current byte transfer, the transfer will

stop and the SS will be deasserted.

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