ADE7169F16 datasheet(130/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 130 of 140

Fcore / 16 = 256kHz if Fcore = 4.096MHz

Fcore / 32 = 128kHz if Fcore = 4.096MHz

Fcore / 64 = 624Hz if Fcore = 4.096MHz

Fcore / 128= 32kHz if Fcore = 4.096MHz

4-0

0xEC –

oxE8

I2CRCT[4:0]

Configures the length of the I2C received FIFO buffer. The I2C peripheral

will stop when I2CRCT[4:0] + 1 bytes have been read or if an error has

occured

Table 130. I2C Slave Address SFR (I2CADR, 0xE9)

Bit

Location

Bit

Mnemonic

Default

Value

Description

7-1

I2CSLVADR

Address of the I2C slave being adressed

Writing to this register start the I2C transmission (Read or write)

I2CR_W

Command bit for Read or Write

When this bit is set to logic one, a read command will be transmitted on

the I2C bus. Data from slave in SPI2CRx SFR is expected after command

byte

When this bit is set to logic zero, a write command will be transmitted on

the I2C bus. Data to slave is expected in SPI2CTx SFR

Table 131. I2C Interrupt Status Register SFR (I2CSTAT, 0xEA)

Bit

Location

Bit

Mnemonic

Default

Value

Description

I2CBUSY

This bit is set to logic one when the I2C interface is used. When set, the Tx

FIFO is emptied

I2CNOACK

I2C no acknlowledgement transmit interrupt

This bit is set to logic one when the slave device did not send an

acknlowledgement. The I2C communication is stopped after this event.

Erased by clearing bit.

I2CRxIRQ

I2C receive interrupt

This bit is set to logic one when the receive FIFO is not empty

This bit is cleared to logic zero by reading the SPI2CRx SFR and the FIFO is

empty

I2CTxIRQ

I2C transmit interrupt

This bit is set to logic one when the transmit FIFO is empty

This bit is cleared to logic zero by writing to the SPI2CTx SFR

3-2

I2CFIFOSTAT[1:0]

Status bit for 3 or 4 bytes deep I2C FIFO. The FIFO monitored in these 2

bits is the one currently used in I2C communication (Receive or Transmit)

as only one of them is active at a time

[1:0]

FIFO empty

Reserved

FIFO Half full

FIFO Full

I2CACC_ERR

Set when trying to write and read at the same time

I2CTxWR_ERR

Set when write was attempted when I2C transmit FIFO was full

An I2C interrupt occurs

* Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C

Patent Rights to use the ADE7XXX in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

READ AND WRITE OPERATIONS

Figure 85 and Figure 86 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select

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