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ADE7169F16 数据表(PDF) 134 Page - Analog Devices |
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ADE7169F16 数据表(HTML) 134 Page - Analog Devices |
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134 / 140 page  ADE7169F16 Preliminary Technical Data Rev. PrD | Page 134 of 140 I/O PORTS PARALLEL I/O The ADE7169F16 uses three input/output ports to exchange data with external devices. In addition to performing general- purpose I/O, some are capable of driving an LCD or performing other alternate functions for the peripheral functions available on-chip. In general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose I/O. The I/O port can be configured through the SFRs in Table 133. Table 133. I/O port SFRs SFR Address Bit Addressable Description P0 0x80 Yes Port 0 register P1 0x90 Yes Port 1 register P2 0xA0 Yes Port 2 register EPCFG 0x9F No Extended Port Configuration PINMAP0 0xB2 No Port 0 weak pull-up enable PINMAP1 0xB3 No Port 1 weak pull-up enable PINMAP2 0xB4 No Port 2 weak pull-up enable The three bidirectional I/O ports have internal pull-ups that can be enabled or disabled individually for each pin. The internal pull-ups are enabled by default. Disabling an internal pull-up causes a pin to become open-drain. Weak internal pull-ups are configured through PINMAPx SFRs. READ LATCH INTERNAL BUS WRITE TO LATCH READ PIN D CL Q LATCH DVDD Px.x PIN INTERNAL PULL-UP ALTERNATE OUTPUT FUNCTION ALTERNATE INPUT FUNCTION Q Closed: PINMAPx.x=0 Open: PINMAPx.x=1 Figure 88. Port 0 Bit Latch and I/O Buffer Figure 88 shows a typical bit latch and I/O buffer for an I/O pin. The bit latch (one bit in the port’s SFR) is represented as a Type D flip-flop, which clocks in a value from the internal bus in response to a write to latch signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a read latch signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU. Some instructions that read a port activate the read latch signal, and others activate the read pin signal. See the Read-Modify-Write Instructions section for details. Weak Internal Pullups Enabled A pin with the weak internal pull-up enabled is used as an input by writing a 1 is written to the pin. The pin will be pulled high by the internal pull-ups and the pin will be read using the circuitry shown in Figure 88. If the pin is driven low externally, it will source current because of the internal pull-ups. If used as an output, a pin with an internal pull-up enabled, will be written with a 1 or a 0 to control the level of the output. If a 0 is written to the pin, it will drive a logic low output voltage (VOL) and is capable of sinking TBD mA. Open Drain (Weak Internal Pull-ups Disabled) When the weak internal pull-up on a pin is disabled, the pin becomes open drain. To use this open-drain pin as a high impedance input, a 1 is written to the pin. The pin will be read using the circuitry shown in Figure 88. The open drain option is preferable for inputs because it draws less current than the internal pull-ups were enabled. To use an open-drain pin as a general purpose output, an external pull-up resistor is required. Open drain outputs are convenient for changing the voltage to a logic high. The ADE7169F16 is a 3.3V device so an external resistor pulled up to 5V may ease interfacing to a 5V IC although most 5V ICs are tolerant of 3.3V inputs. Pins with 0s written to them drive a logic low output voltage (VOL) and are capable of sinking 1.6 mA. 38 kHz Modulation The ADE7169F16 provides a 38 kHz modulation signal. The 38 kHz modulation is accomplished by internally XORing the level written to the MOD38 pin with a 38 kHz square wave. Then when a zero is written to the MOD38 pin, it is modulated as shown in Figure 89. 38kHz Modulation Signal Output at MOD38 Pin Level written to MOD38 Figure 89: 38 kHz Modulation Uses for this 38 kHz modulation include IR modulation of a UART transmit signal or a low power signal to drive a LED. The modulation can be enabled or disabled with the MOD38EN bit in the CFG SFR. The 38 kHz modulation is available on eight pins, selected by the MOD38[7:0] bits in the Extended Port Configuration SFR (EPCFG, 0x9F). |
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