ADE7169F16 datasheet(137/140 Pages) AD

137 / 140 page

Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 137 of 140

P0.5

MISO SPI Data line

Set the SCPS bit in the Configuration SFR (CFG, 0xAF) and set

the SPIEN bit in the SPI Configuration Register SFR

(SPIMOD2, 0xE9)

SCLK serial clock for I2C or SPI

Set the I2CEN bit in the I2CMOD SFR or the SPIEN bit in the

SPI Configuration Register SFR (SPIMOD2, 0xE9) to enable

the I2C or SPI interface

P0.6

T0 Timer0 input

Set the CNT0 bit in the Timer/Counter 0 and 1 Mode SFR

(TMOD, 0x89) to enable T0 as an external event counter

SS SPI slave select input for SPI in slave mode

Set the SS_EN bit in the SPI Configuration Register SFR

(SPIMOD1, 0xE8)

SS SPI slave select output for SPI in master

mode

Set the SPIMS_b bit in the SPI Configuration Register SFR

(SPIMOD2, 0xE9)

P0.7

T1 Timer 1 input

Set the CNT1 bit in the Timer/Counter 0 and 1 Mode SFR

(TMOD, 0x89) to enable T1 as an external event counter

Table 142. Port 1 Alternate Functions

No.

Alternate Function

Alternate Function Enable

RxD Receiver Data Input for UART

Set the REN bit in the SCON SFR Bit Description SFR (SCON,

0x98).

P1.0

RX Edge wakeup from PSM2 operating mode

Set RXPROG[1:0]=11 in the Peripheral Configuration SFR

(PERIPH, 0xF4)

P1.1

TxD Transmitter Data Output for UART

P1.2

FP25 LCD Segment Pin

Set FP25EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

FP24 LCD Segment Pin

Set FP24EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.3

T2EX Timer 2 control input

Set EXEN2 in the Timer/Counter 2 Control SFR (T2CON, 0xC8)

FP23 LCD Segment Pin

Set FP23EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.4

T2 Timer 2 input

Set the CNT2 bit in the Timer/Counter 2 Control SFR (T2CON,

0xC8) to enable T2 as an external event counter

P1.5

FP22 LCD Segment Pin

Set FP22EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.6

FP21 LCD Segment Pin

Set FP21EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

P1.7

FP20 LCD Segment Pin

Set FP20EN in the LCD Segment Enable SFR (LCDSEGE, 0x97)

Table 143. Port 2 Alternate Functions

No.

Alternate Function

Alternate Function Enable

P2.0

FP18 LCD Segment Pin

Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

P2.1

FP17 LCD Segment Pin

Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

P2.2

FP16 LCD Segment Pin

Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2,

0xED)

P2.3

SDEN Serial Download pin sampled on reset.

P2.3 is an output only.

Enabled by default.

PORT 0

Port 0 is controlled directly through the bit-addressable Port 0 SFR (80H). The weak internal pull-ups for Port 0 are configured through

the Port 0 Weak pull-up enable SFR (PINMAP0, 0xB2); they are enabled by default. Disable the weak internal pull-up by writing a one to

P0CFG..x.

Port 0 pins also have various secondary functions as described in Table 141. The alternate functions of Port 0 pins can be activated only if

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