AD9981SLASHPCB datasheet(31/44 Pages) AD

31 / 44 page

AD9981

Rev. 0 | Page 31 of 44

0x10

7:5

Blue Channel Offset LSBs

The LSBs of the blue channel offset control combine

with the 8 bits of MSB in the previous register to make

11 bits of offset control.

HSYNC CONTROLS

0x11

7:0

Sync Separator Threshold

This register sets the threshold of the sync separator’s

digital comparator. The value written to this register is

multiplied by 200 ns to get the threshold value.

Therefore, if a value of 5 is written, the digital

comparator threshold is 1 µs and any pulses less than 1

µS are rejected by the sync separator. There is some

variability to the 200 ns multiplier value. The

maximum variability over all operating conditions is

±20% (160 ns to 240 ns). Since normal Vsync and

Hsync pulse widths differ by a factor of about 500 or

more, the 20% variability is not an issue. The power-

up default value is 32 DDR.

0x12

Hsync Source Override

This is the active Hsync override. Setting this to 0

allows the chip to determine the active Hsync source.

Setting it to 1 uses Bit 6 of Register 0x12 to determine

the active Hsync source. Power-up default value is 0.

Table 16.Active Hsync Source Override

Override

Result

Hsync Source determined by chip

Hsync Source determined by user

0x12

Hsync Source

This bit selects the source of the Hsync for PLL and

sync processing—only if Bit 7 of Register 0x12 is set to

1 or if both syncs are active. Setting this bit to 0

specifies the Hsync from the input pin. Setting it to 1

selects Hsync from SOG. Power-up default is 0.

Table 17. Active Hsync Select Settings

Select

Result

Hsync Input

Hsync from SOG

0x12

Hsync Input Polarity Override

This bit determines whether the chip selects the Hsync

input polarity or if it is specified. Setting this bit to 0

allows the chip to automatically select the polarity of

the input Hsync; setting it to 1 indicates that Bit 4 of

is 0.

Table 18. Hsync Input Polarity Override Settings

Override Bit

Result

Hsync Polarity Determined by Chip

Hsync Polarity Determined by User

0x12

Input Hsync Polarity

If Bit 5 of Register 0x12 is 1, the value of this bit

specifies the polarity of the input Hsync. Setting this

bit to 0 indicates an active low Hsync; setting this bit

to 1 indicates an active high Hsync. Power-up default

is 1.

Table 19. Hsync Input Polarity Settings

Hsync Polarity Bit

Result

Hsync Input Polarity is Negative

Hsync Input Polarity is Positive

0x12

Hsync Output Polarity

This bit sets the polarity of the Hsync output. Setting

this bit to 0 sets the Hsync output to active low. Setting

this bit to 1 sets the Hsync output to active high.

Power-up default setting is 1.

Table 20. Hsync Output Polarity Settings

Hsync Output

Polarity Bit

Result

Hsync Output Polarity is Negative

Hsync Output Polarity is Positive

0x13

7:0

Hsync Duration

An 8-bit register that sets the duration of the Hsync

output pulse. The leading edge of the Hsync output is

triggered by the internally-generated, phase-adjusted

PLL feedback clock. The AD9981 then counts a

number of pixel clocks equal to the value in this

output, which is also phase-adjusted.

VSYNC CONTROLS

0x14

Vsync Source Override

This is the active Vsync override. Setting this to 0

allows the chip to determine the active Vsync source,

setting it to 1 uses Bit 6 of Register 0x14 to determine

the active Vsync source. Power-up default value is 0.

Table 21. Active Vsync Source Override

Override

Result

Vsync source determined by chip

Vsync source determined by user

AD9981/PCB 数据表(PDF) 31 Page - Analog Devices

AD9981/PCB 数据表(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载

链接网址

AD9981/PCB 数据表(PDF) 31 Page - Analog Devices

AD9981/PCB 数据表(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表 下载

链接网址

数据表下载