AD9981

Rev. 0 | Page 9 of 44

Pin

Description

REFLO

REFCM

REFHI

Input Amplifier Reference.

REFLO and REFHI are connected together through a 10 µF capacitor; REFCM is connected through a 10 µF capacitor to

ground. These are used for stability in the input PGA (programmable gain amplifier) circuitry. See Figure 4.

FILT

External Filter Connection.

For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 5to

this pin. For optimal performance, minimize noise and parasitics on this node. For more information, see the PCB

Layout Recommendations section.

OUTPUTS

HSOUT

Horizontal Sync Output.

A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be

programmed via serial bus registers. By maintaining alignment with DATACK and Data Output, data timing with

respect to Hsync can always be determined.

VSOUT/A0

Vertical Sync Output.

Pin shared with A0, serial port address. This can be either a separated Vsync from a composite signal or a direct pass

through of the Vsync signal. The polarity of this output can be controlled via a serial bus bit. The placement and

duration in all modes can be set by the graphics transmitter or the duration can be set by Register 0x14 and Register

0x15. This pin is shared with the A0 function, which does not affect Vsync Output functionality. For more details on

A0, see the description in the Serial Control Port section.

SOGOUT

Sync-On-Green Slicer Output.

This pin outputs one of four possible signals (controlled by Register 0x1D, Bits [1:0]): raw SOG, raw Hsync, regenerated

Hsync from the filter, or the filtered Hsync. See the sync processing block diagram (see Figure 8) to view how this pin

is connected. Other than slicing off SOG, the output from this pin gets no other additional processing on the AD9981.

Vsync separation is performed via the sync separator.

O/E FIELD

Odd/Even Field Bit for Interlaced Video. This output will identify whether the current field (in an interlaced signal) is

odd or even.

SERIAL PORT

SDA

Serial Port Data I/O.

SCL

Serial Port Data Clock.

VSOUT/A0

Serial Port Address Input 0.

Pin shared with VSOUT. This pin selects the LSB of the serial port device address, allowing two Analog Devices parts to

be on the same serial bus. A high impedance external pull-up resistor enables this pin to be read at power-up as 1, or

a high impedance, external pull-down resistor enables this pin to be read at power-up as a 0 and not interfere with

the VSOUT functionality. For more details on VSOUT, see the Data Outputs section in this table.

DATA OUTPUTS

RED [9:0]

Data Output, Red Channel.

GREEN [9:0]

Data Output, Green Channel.

BLUE [9:0]

Data Output, Blue Channel.

The main data outputs.

Bit 9 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by

adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so

the timing relationship among the signals is maintained.

DATA CLOCK

OUTPUT

DATACK

Data Clock Output.

This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible

output clocks can be selected with Register 0x20, Bits [7:6]. Three of these are related to the pixel clock (pixel clock,

90° phase-shifted pixel clock and 2× frequency pixel clock). They are produced either by the internal PLL clock

generator or EXTCLK and are synchronous with the pixel sampling clock. The fourth option for the data clock output is

an internally generated 40 MHz clock.

The sampling time of the internal pixel clock can be changed by adjusting the phase register (Register 0x04). When

this is changed, the pixel related DATACK timing is also shifted. The Data, DATACK, and HSOUT outputs are all moved

so that the timing relationship among the signals is maintained.