AD9981SLASHPCB datasheet(13/44 Pages) AD

13 / 44 page

AD9981

Rev. 0 | Page 13 of 44

Negative target codes are included in order to duplicate a fea-

ture that is present with manual offset adjustment. The benefit

that is being mimicked is the ability to easily adjust brightness

on a display. By setting the target code to a value that does not

correspond to the ideal ADC range, the end result is an image

that is either brighter or darker. A target code higher than ideal

results in a brighter image, while a target code lower than ideal

results in a darker image.

The ability to program a target code gives a large degree of

freedom and flexibility. While in most cases all channels are set

to either 1 or 512, the flexibility to select other values allows the

possibility of inserting intentional skews between channels. It

also allows the ADC range to be skewed so that voltages outside

of the normal range can be digitized. For example, setting the

target code to 40 allows the sync tip, which is normally below

black level, to be digitized and evaluated.

The internal logic for the auto-offset circuit requires 16 data

clock cycles to perform its function. This operation is executed

immediately after the clamping pulse. Therefore, it is important

to end the clamping pulse signal at least 16 data clock cycles

before active video. This is true whether using the AD9981’s

internal clamp circuit or an external clamp signal. The auto-

offset function can be programmed to run continuously or on a

one-time basis (see auto-offset hold, Register 0x2C, Bit 4). In

continuous mode, the update frequency can be programmed

(Register 0x1B, Bits [4:3]). Continuous operation with updates

every 64 Hsyncs is recommended.

A guideline for basic auto-offset operation is shown in Table 5

and Table 6.

Table 5. RGB Auto-Offset Register Settings

Value

Comments

0x0B

0x00

Sets red target to 4

0x0C

0x80

Must be written

0x0D

0x00

Sets green target to 4

0x0E

0x80

Must be written

0x0F

0x00

Sets blue target to 4

0x10

0x80

Must be written

0x18, Bits [3:1]

000

Sets red, green, and blue

channels to ground clamp

0x1B, Bit [5:3]

110

Selects update rate and

enables auto-offset.

Table 6. PbPr Auto-Offset Register Settings

Value

Comments

0x0B

0x40

Sets Pr (red) target to 512

0x0C

0x00

Must be written

0x0D

0x00

Sets Y (green) target to 4

0x0E

0x80

Must be written

0x0F

0x40

Sets Pb (blue) target to 512

0x10

0x00

Must be written

0x18 Bits [3:1]

101

Sets Pb, Pr to midscale clamp

and Y to ground clamp

0x1B, Bit [5:3]

110

Selects update rate and

enables auto-offset.

Sync-on-Green

The sync-on-green input operates in two steps. First, it sets a

baseline clamp level off of the incoming video signal with a

negative peak detector. Second, it sets the sync trigger level to

a programmable (Register 0x1D, Bits [7:3]) level (typically

128 mV) above the negative peak. The sync-on-green input

must be ac-coupled to the green analog input through its own

capacitor. The value of the capacitor must be 1 nF ±20%. If

sync-on-green is not used, this connection is not required. The

sync-on-green signal always has negative polarity.

RAIN

BAIN

GAIN

SOG

47nF

1nF

Figure 4. Typical Input Configuration

Reference Bypassing

REFLO and REFHI are connected to each other by a 10 µF

capacitor. REFCM is connected to ground by a 10 µF capacitor.

These references are used by the input PGA circuitry.

REFHI

REFLO

REFCM

µF

Figure 5. Input Amplifier Reference Capacitors

Clock Generation

A PLL is used to generate the pixel clock. The Hsync input

provides a reference frequency to the PLL. A voltage-

controlled oscillator (VCO) generates a much higher pixel clock

frequency. The pixel clock is divided by the PLL divide value

(Register 0x01 and Register 0x02) and phase-compared with the

Hsync input. Any error is used to shift the VCO frequency and

maintain lock between the two signals.

The stability of this clock is a very important element in

providing the clearest and most stable image. During each pixel

time, there is a period when the signal is slewing from the old

pixel amplitude and settling at its new value. Then there is a

time when the input voltage is stable, before the signal must

slew to a new value (see Figure 6). The ratio of the slewing time

to the stable time is a function of the bandwidth of the graphics

DAC and the bandwidth of the transmission system (cable and

termination). It is also a function of the overall pixel rate.

Clearly, if the dynamic characteristics of the system remain

fixed, then the slewing and settling time is likewise fixed. This

time must be subtracted from the total pixel period, leaving the

stable period. At higher pixel frequencies, the total cycle time is

shorter and the stable pixel time also becomes shorter.

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