AD9981SLASHPCB datasheet(36/44 Pages) AD

36 / 44 page

AD9981

Preliminary Technical Data

Rev. 0 | Page 36 of 44

0x1F

Secondary Output Enable

This bit places the secondary output in active or high

impedance mode.

The secondary output is designated when using either

4:2:2 or 4:4:4 (DDR). In these modes, the data on the

blue output channel is the secondary output while the

output data on the red and green channels are the

primary output. Secondary output is always a DDR

YCbCr data mode. See the Output Formatter section

and Table 11. The power-up default setting is 0.

Table 45. Secondary Output Enable

Select

Result

Secondary output is in high impedance mode

Secondary output is enabled

0x1F

2:1

Output Drive Strength

These two bits select the drive strength for all the

high-speed digital outputs (except VSOUT, A0, and

the O/E field). Higher drive strength results in faster

rise/fall times and in general makes it easier to capture

data. Lower drive strength results in slower rise/fall

times and helps to reduce EMI and digitally generated

power supply noise. The power-up default setting

is 10.

Table 46. Output Drive Strength

Output Drive

Result

Low output drive strength

Medium low output drive strength

Medium high output drive strength

High output drive strength

0x1F

Output Clock Invert

This bit allows inversion of the output clock. The

power-up default setting is 0.

Table 47. Output Clock Invert

Select

Result

Noninverted pixel clock

Inverted pixel clock

0x20

7:6

Output Clock Select

These bits allow selection of optional output clocks

such as a fixed 40 MHz clock, a 2× clock, a 90° phase-

shifted clock, or the normal pixel clock. The power-up

default setting is 00.

Table 48. Output Clock Select

Select

Result

Pixel clock

90° phase-shifted pixel clock

2× pixel clock

40 MHz internal clock

0x20

Output High Impedance

This bit puts all outputs (except SOGOUT) in a high impedance

state. The power-up default setting is 0.

Table 49. Output High Impedance

Select

Result

Normal outputs

All outputs (except SOGOUT) in high impedance

mode

0x20

SOG High Impedance

This bit allows the SOGOUT pin to be placed in high

impedance mode. The power-up default setting is 0.

Table 50. SOGOUT High Impedance

Select

Result

Normal SOG output

SOGOUT pin is in high impedance mode

0x20

Field Output Polarity

This bit sets the polarity of the field output bit. The

power-up default setting is 1.

Table 51. Field Output Polarity

Select

Result

Active low = even field; active high = odd field

Active low = odd field; active high = even field

SYNC PROCESSING

0x20

PLL Sync Filter

This bit selects which signal the PLL uses. It can select

between either raw Hsync or SOG or filtered versions.

The filtering of the Hsync and SOG can eliminate

nearly all extraneous transitions which have tradi-

tionally caused PLL disruption. The power-up default

setting is 0.

Table 52. PLL Sync Filter Enable

Select

Result

PLL uses raw Hsync or SOG inputs

PLL uses filtered Hsync or SOG inputs

0x20

Sync Processing Input Source

This bit selects whether the sync processor uses a raw

sync or a regenerated sync for the following functions:

Coast, H/V count, field detection and Vsync duration

counts. Using the regenerated sync is recommended.

Table 53. SP Filter Enable

Select

Result

Sync processing uses raw Hsync or SOG

Sync processing uses the internally regenerated

Hsync

AD9981/PCB 数据表(PDF) 36 Page - Analog Devices

AD9981/PCB 数据表(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载

链接网址

AD9981/PCB 数据表(PDF) 36 Page - Analog Devices

AD9981/PCB 数据表(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表 下载

链接网址

数据表下载