AD9981

Rev. 0 | Page 23 of 44

TWO-WIRE SERIAL REGISTER MAP

The AD9981 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to

write and read the control registers through the two-wire serial interface port.

Table 12. Control Register Map

Hexadecimal

Address

Read and

Write or

Read Only

Bits

Default

Value

Register Name

Description

0x00

RO

7:0

Chip Revision

An 8-bit register that represents the silicon revision level.

0x01

R/W

7:0

0110 1001

PLL Div MSB

This register is for bits [11:4] of the PLL divider. Larger values

mean the PLL operates at a faster rate. This register should be

loaded first whenever a change is needed. (This will give the PLL

more time to lock.)1

0x02

R/W

7:4

1101 ****

PLL Div LSB

Bits [7:4] LSBs of the PLL Divider Word. Links to the PLL Div MSB

to make a 12-bit register.

1

0x03

R/W

7:6

01** ****

VCO/CPMP

Bits [7:6] VCO Range. Selects VCO frequency range.

(See PLL description).

5:3

**00 1***

Bits [5:3] Charge Pump Current. Varies the current that drives the

low-pass filter. (See PLL description).

2

**** *0**

Bit 2. External Clock Enable.

0x04

R/W

7:3

1000 0***

Phase Adjust

ADC Clock Phase Adjustment. Larger values mean more delay.

(1 LSB = T/32).

0x05

R/W

6:0

*100 0000

Red Gain MSBs

7-Bit Red Channel Gain Control. Controls ADC input range

(contrast) of each respective channel. Bigger values give less

contrast.

0x06

R/W

7:0

00** ****

Red Gain LSBs

Linked with Register 0x05 to form the 9-bit red gain that controls

the ADC input range (contrast) of the red channel. A lower value

corresponds to a higher gain.

1

0x07

R/W

6:0

*100 0000

Green Gain

MSBs

7-Bit Green Channel Gain Control. Controls ADC input range

(contrast) of each respective channel. Bigger values give less

contrast.

0x08

R/W

7:0

00** ****

Green Gain LSBs

Linked to Register 0x07 to form the 9-bit green gain that controls

the ADC input range (contrast) of the green channel. A lower

value corresponds to a higher gain.

1

0x09

R/W

6:0

*100 0000

Blue Gain MSBs

7-Bit Blue Channel Gain Control. Controls ADC input range

(contrast) of each respective channel. Bigger values give less

contrast.

0x0A

R/W

7:0

00** ****

Blue Gain LSBs

Linked to Register 0x09 to form the 9-bit blue gain that controls

the ADC input range (contrast) of the blue channel. A lower value

corresponds to a higher gain.

1

0x0B

R/W

7:0

0100 0000

Red Offset MSBs

8-Bit MSBs of the Red Channel Offset Control. Controls dc offset

(brightness) of each respective channel. Bigger values decrease

brightness.

1

0x0C

R/W

7

000* ****

Red Offset LSBs

Linked to Register 0x0B to form the 11-bit red offset that controls

the dc offset (brightness) of the red channel in auto-offset mode.

0x0D

R/W

7:0

0100 0000

Green Offset

MSBs

8-Bit MSBs of the Green Channel Offset Control. Controls dc

offset (brightness) of each respective channel. Bigger values

decrease brightness.

1

0x0E

R/W

7

000* ****

Green Offset

LSBs

Linked to Register 0x0D to form the 11-bit green offset that

controls the dc offset (brightness) of the green channel in auto-

offset mode.

0x0F

R/W

7:0

0100 0000

Blue Offset MSBs

8-Bit MSBs of the Red Channel Offset Control. Controls dc offset

(brightness) of each respective channel. Bigger values decrease

brightness.

1

0x10

R/W

7

000* ****

Blue Offset LSBs

Linked to Register 0x0F to form the 11-bit blue offset which

controls the dc offset (brightness) of the blue channel in auto-

offset mode.