AD9981SLASHPCB datasheet(38/44 Pages) AD

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AD9981

Preliminary Technical Data

Rev. 0 | Page 38 of 44

POLARITY STATUS

0x25

Hsync0 Polarity

Indicates the polarity of the HSYNC0 input.

Table 62. Detected Hsync0 Polarity Results

Detect

Result

Hsync polarity is negative

Hsync polarity is positive

0x25

Hsync1 Polarity

Indicates the polarity of HSYNC1 input.

Table 63. Detected Hsync1 Polarity Results

Detect

Result

Hsync polarity is negative

Hsync polarity is positive

0x25

Vsync0 Polarity

Indicates the polarity of Vsync0 input.

Table 64. Detected Vsync0 Polarity Results

Detect

Result

Vsync polarity is negative

Vsync polarity is positive

0x25

Vsync1 Polarity

Indicates the polarity of Vsync1 input.

Table 65. Detected Vsync1 Polarity Results

Detect

Result

Vsync polarity is negative

Vsync polarity is positive

0x25

Coast Polarity

Indicates the polarity of the external Coast signal.

Table 66. Detected Coast Polarity Results

Detect

Result

Coast polarity is negative

Coast polarity is positive

0x25

Clamp Polarity

Indicates the polarity of the clamp signal.

Table 67. Detected Clamp Polarity Results

Detect

Result

Clamp polarity is negative

Clamp polarity is positive

0x25

Extraneous Pulses Detection

A second output from the Hsync filter, this status bit

tells whether extraneous pulses are present on the

incoming sync signal. Often extraneous pulses are

used for copy protection, so this status bit can be used

for this purpose.

Table 68. Equalization Pulse Detect Bit

Detect

Result

No equalization pulses detected during active

Hsync

Equalization pulses detected during active Hsync

HSYNC COUNT

0x26

7:0

Hsyncs/Vsync MSB

The eight MSBs of the 12-bit counter that reports the

number of Hsyncs/Vsync on the active input. This is

useful for determining the mode and is an aid in

setting the PLL divide ratio.

0x27

7:4

Hsyncs/Vsync LSBs

The four LSBs of the 12-bit counter that reports the

number of Hsyncs/Vsync on the active input.

Test Registers

0x28

7:0

Test Register 0

Must be written to 0xBF for proper operation.

0x29

7:0

Test Register 1

Must be written to 0x00 for proper operation.

0x2A

7:0

Test Register 2

Read-only bits for future use.

0x2B

7:0

Test Register 3

Read-only bits for future use.

0x2C

7:0

Test Register 4

Must be written to 0x00 for proper operation.

0x2C

Auto-Offset Hold

A bit for controlling whether the auto-offset function

runs continuously or runs once and holds the result.

Continuous updates are recommended because it

allows the AD9981 to compensate for drift-over time,

temperature, and so on. If one-time updates are

preferred, these should be performed every time the

part is powered up and when there is a mode change.

To do a one-time update, first auto-offset must be

enabled (0x1B, Bit 5). Next, this bit (auto-offset hold)

must be set to 1 to let the auto-offset function operate

and settle to a final value. Auto-offset hold should then

be set to 0 to hold the offset values that the auto

circuitry calculates. The AD9981’s auto-offset circuit’s

maxi-mum settle time is 10 updates. For example, if

the update frequency is set to once every 64 Hsyncs,

then the maximum settling time would be 640 Hsyncs

(10 × 64 Hsyncs).

AD9981/PCB 数据表(PDF) 38 Page - Analog Devices

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AD9981/PCB 数据表(PDF) 38 Page - Analog Devices

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