AD9981SLASHPCB datasheet(33/44 Pages) AD

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AD9981

Rev. 0 | Page 33 of 44

Table 28. Coast Source Selection Settings

Select

Result

Vsync (internal Coast)

COAST input pin

0x18

Coast Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Coast signal going

into the PLL. The power-up default setting is 0.

Table 29. Coast Polarity Override Settings

Override Bit

Result

Coast polarity determined by chip

Coast polarity determined by user

0x18

Input Coast Polarity

This register sets the input Coast polarity when Bit 6

of Register 0x18 = 1. The power-up default setting is 1.

Table 30. Coast Polarity Settings

Coast Polarity Bit

Result

Coast polarity is negative

Coast polarity is positive

0x18

Clamp Source

This bit determines the source of clamp timing. A 0

enables the clamp timing circuitry controlled by

clamp placement and clamp duration. The clamp posi-

tion and duration is counted from the leading edge of

Hsync. A 1 enables the external clamp input pin. The

three channels are clamped when the clamp signal is

active. The polarity of clamp is determined by the

clamp polarity bit. The power-up default setting

is 0.

Table 31. Clamp Source Selection Settings

Clamp Source

Result

Internally generated clamp

Externally provided clamp signal

0x18

Red Clamp Select

This bit determines whether the red channel is

clamped to ground or to midscale. The power-up

default setting is 0.

Table 32. Red Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x18

Green Clamp Select

This bit determines whether the green channel is

clamped to ground or to midscale. The power-up

default setting is 0.

Table 33. Green Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x18

Blue Clamp Select

This bit determines whether the blue channel is

clamped to ground or to midscale. The power-up

default setting is 0.

Table 34. Blue Clamp Select Settings

Clamp

Result

Clamp to ground

Clamp to midscale

0x19

7:0

Clamp Placement

An 8-bit register that sets the position of the internally

generated clamp. When EXTCLMP = 0 (Register 0x18,

Bit 4), a clamp signal is generated internally, at a

position established by the clamp placement register

(Register 0x19) and for a duration set by the clamp

duration register (Register 0x1A). Clamping is started

a clamp placement count(Register 0x19) of pixel

periods after the trailing edge of Hsync. The clamp

placement may be programmed to any value between

1 and 255. A value of 0 is not supported.

The clamp should be placed during a time that the

input signal presents a stable black-level reference,

usually the back porch period between Hsync and the

image. When EXTCLMP = 1, this register is ignored.

Power-up default setting is 8.

0x1A

7:0

Clamp Duration

An 8-bit register that sets the duration of the

internally generated clamp. When EXTCLMP = 0

(Register 0x18, Bit 4), a clamp signal is generated

internally at a position established by the clamp

placement register (and for a duration set by the

clamp duration register). Clamping begins a clamp

placement count (Register 0x19) of pixel periods after

the trailing edge of Hsync. The clamp duration may be

programmed to any value between 1 and 255. A value

of 0 is not supported.

For the best results, the clamp duration should be set

to include the majority of the black reference signal

time that follows the Hsync signal trailing edge. Insuf-

ficient clamping time can produce brightness changes

at the top of the screen, and a slow recovery from large

changes in the average picture level (APL), or bright-

ness. When EXTCLMP = 1, this register is ignored.

Power-up default setting is 20 DDR.

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